View SED1354_4146713.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SED1354 Color Graphics LCD/CRT Controller
SED1354 TECHNICAL MANUAL
Document Number: X19A-Q-002-10
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-Q-002-10
TECHNICAL MANUAL Issue Date: 98/11/27
Epson Research and Development Vancouver Design Center
Page 3
Customer Support Information
Comprehensive Support Tools
Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems.
Evaluation / Demonstration Board
* Assembled and fully tested graphics evaluation board with installation guide and schematics. * To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative.
Chip Documentation
* Technical manual includes Data Sheet, Application Notes, and Programmer's Reference.
Software
* OEM Utilities. * User Utilities. * Evaluation Software. * To obtain these programs, contact Application Engineering Support.
Application Engineering Support
Engineering and Sales Support is provided by:
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346
North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com
Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
TECHNICAL MANUAL Issue Date: 98/11/27
SED1354 X19A-Q-002-10
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-Q-002-10
TECHNICAL MANUAL Issue Date: 98/11/27
Epson Research and Development Vancouver Design Center
Page 5
Table of Contents
INTRODUCTION SED1354 Color Graphics LCD / CRT Controller Product Brief SPECIFICATION SED1354 Hardware Functional Specification PROGRAMMER'S REFERENCE SED1354 Programming Notes and Examples SED1354 Register Summary UTILITIES 1354CFG.EXE File Configuration Program 1354SHOW Demonstration Program 1354SPLT Display Utility 1354VIRT Display Utility 1354PLAY Diagnostic Utility 1354BMP Demonstration Program 1354PWR Software Suspend Power Sequencing Utility DRIVERS Windows(R) CE Display Drivers EVALUATION SDU1354B0C Rev. 1 ISA Bus Evaluation Board User Manual SDU1354-D9000 Evaluation Board User Guide APPLICATION NOTES Power Consumption Interfacing to the Philips MIPS PR31500/PR31700 Processor Interfacing to the NEC VR4102 Microprocessor Interfacing the SED1354 to the Motorola MCF5307 Microprocessor Interfacing the SED1354/55 to the Motorola MC68328 Microprocessor Interfacing the SED1354 to the Motorola MPC821 Microprocessor Interfacing the SED1354 to the PC Card Bus Interfacing to the Toshiba MIPS TX3912 Processor
TECHNICAL MANUAL Issue Date: 98/11/27
SED1354 X19A-Q-002-10
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-Q-002-10
TECHNICAL MANUAL Issue Date: 98/11/27
ENERGY S AV I NG
EPSON
GRAPHICS SED1354
October 1998
SED1354 COLOR GRAPHICS LCD/CRT CONTROLLER
s DESCRIPTION
The SED1354 is a low cost, low power, color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The SED1354 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows(R) CE may serve as a primary operating system. The SED1354 supports LCD interfaces with data widths up to 16-bits. Using Frame Rate Modulation (FRM), it can display 16 shades of gray on monochrome LCD panels, up to 4096 colors on passive color LCD, and 64K colors on active matrix TFT LCD panels. CRT support is handled through the use of an external RAMDAC interface allowing simultaneous display of both the CRT and LCD panel. A 16-bit memory interface supports up to 2M bytes of FPMDRAM or EDO-DRAM. Supports flexible operating voltages from 2.7V to 5.5V.
s FEATURES
Memory Interface * 16-bit EDO-DRAM or FPM-DRAM interface. * Memory size options: 512K bytes using one 256Kx16 device. 2M bytes using one 1Mx16 device. * Addressable as a single linear address space. CPU Interface * Supports the following interfaces: Hitachi SH-3. Motorola M68K. ISA bus. MPU bus interface with programmable READY. i386/486 bus. Philips MIPS PR31500/31700. NEC MIPS VR4102. * CPU write buffer. Display Support * 4/8-bit monochrome passive LCD interface. * 4/8/16-bit color passive LCD interface. * Single-panel, single-drive displays. * Dual-panel, dual-drive displays. * Direct support for 9/12-bit TFT; 18-bit TFT is supported up to 64K color depth (16-bit data). * External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel data bus. * Simultaneous display of CRT and 4/8-bit passive or 9-bit TFT panels, regardless of resolution. * Maximum resolution of 800x600 pixels at a color depth of 16 bpp.
Display Modes * 1/2/4/8/16 bit-per-pixel (bpp) support on LCD. * 1/2/4/8 bit-per-pixel (bpp) on CRT. * Up to 16 shades of gray using FRM on monochrome passive LCD panels. * Up to 4096 colors on passive LCD panels. * Up to 64K colors on active matrix TFT LCD in 16 bpp modes. * Split Screen Display: allows two different images to be simultaneously displayed. * Virtual Display Support: displays images larger than the panel size through the use of panning. * Double Buffering/multi-pages: provides smooth animation and instantaneous screen update. * Acceleration of screen updates by allocating full display buffer bandwidth to CPU. Clock Source * Single clock input for both pixel and memory clocks. * Memory clock can be input clock or (input clock/2), providing flexibility to use CPU bus clock as input. * Pixel clock can be memory clock or (memory clock/ 2), (memory clock/3) or (memory clock/4). Power Down Modes * Two power down modes: one software / one hardware. * LCD Power Sequencing. General Purpose IO pins * Up to 12 General Purpose IO pins are available. Operating Voltage * 2.7 volts to 5.5 volts. Package * 128-pin QFP15 surface mount package
X19A-C-002-10
1
GRAPHICS SED1354
s SYSTEM BLOCK DIAGRAM
RAMDAC
EDO-DRAM FPM-DRAM
Analog Out
CRT Control
CPU
Clock
SED1354
Digital Out
Flat Panel
Actual Size
CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS: * SED1354 Technical Manual * SDU1354 Evaluation Boards * Windows(R) CE Display Driver * CPU Independent Software Utilities
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com.com
FOR SYSTEM INTEGRATION SERVICES FOR WINDOWS(R) CE CONTACT: Epson Research & Development, Inc. Suite #320 - 11120 Horseshoe Way Richmond, B.C., Canada V7A 5H7 Tel: (604) 275-5151 Fax: (604) 275-2167 Email: wince@erd.epson.com http://www.erd.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
Copyright (c)1997, 1998 Epson Research and Development, Inc. All rights reserved. VDC Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/ EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. Microsoft, Windows, and the Windows CE Logo are registered trademarks of Microsoft Corporation.
2
X19A-C-002-10
SED1354 Color Graphics LCD/CRT Controller
Hardware Functional Specification
Document Number: X19A-A-002-16
Copyright (c) 1997, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 1.2 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 4 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Display Support Clock Source Package and Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Block Description 4.1 4.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Functional Block Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Display FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power Save . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Pin Out 5.1 5.2 5.3 5.4
Pinout Diagram for SED1354F0A . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pinout Diagram for SED1354F1A . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pinout Diagram for SED1354F2A . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CRT and External RAMDAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5 5.6 6 7
Summary of Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Multiple Function Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.1.1 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 4
Epson Research and Development Vancouver Design Center
7.1.2 7.1.3 7.1.4 7.1.5 7.2 7.3
MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . . . . . . . . . .38 MC68K Bus 2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . . . . . . . . . .40 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . .42 Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . .44
Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Memory Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 7.3.9 7.3.10 EDO-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 EDO-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . .53 EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 FPM-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . .61 FPM-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 16-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 External RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.4
Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.4.12 7.4.13 7.4.14
8
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 8.1 8.2 Register Mapping 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Revision Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Memory Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Panel/Monitor Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Display Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 5
8.2.9 9 9.1 9.2
External RAMDAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Image Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Half Frame Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
10 Display Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 10.1 Display Mode Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 10.2 Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 11 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 11.1 Maximum MCLK: PCLK Ratios . . . . . . . . . . . . . . . . . . . . . . . . . . .119 11.2 Frame Rate Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 12 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 12.1 Gray Shade Display Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 12.2 Color Display Modes 13.1 Hardware Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 13 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 13.2 Software Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 13.3 Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . .129 13.4 Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . .129 14 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 14.1 QFP15-128 (SED1354F0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 14.2 TQFP15-128 (SED1354F1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 14.3 QFP20-144 (SED1354F2A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 7
List of Tables
Table 2-1: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Table 5-5: Table 5-6: Table 5-7: Table 5-8: Table 5-9: SED1354 Series Package list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Memory Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Clock Input Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 CRT and RAMDAC Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power Supply Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Summary of Power On / Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5-10: Memory Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6-1: Table 6-2: Table 6-3: Table 6-4: Table 7-1: Table 7-2: Table 7-3: Table 7-4: Table 7-5: Table 7-6: Table 7-7: Table 7-8: Table 7-9: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Input Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Output Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EDO DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 EDO DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 EDO DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 7-10: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 7-11: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 7-12: FPM DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 7-13: FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 7-14: FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 7-16: FPM-DRAM CBR Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 7-17: LCD Panel Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 7-18: LCD Panel Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Table 7-21: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 7-24: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 8
Epson Research and Development Vancouver Design Center
Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Table 7-26: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Table 7-27: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Table 7-28: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 Table 7-29: CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Table 7-30: Generic Bus RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 Table 8-1: Table 8-2: Table 8-3: Table 8-4: Table 8-5: Table 8-6: Table 8-7: Table 8-8: Table 8-9: SED1354 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 DRAM Refresh Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Panel Data Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 FPLINE Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 FPFRAME Polarity Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Simultaneous Display Option Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Number of Bits-Per-Pixel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Pixel Panning Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 8-10: Suspend Refresh Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 8-11: Minimum Memory Timing Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Table 8-12: RAS-to-CAS Delay Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 8-13: RAS Precharge Timing Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency . . . . . . . . . . . . . 109 Table 8-15: RGB Index Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 9-1: SED1354 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 11-1: Maximum PCLK Frequency with EDO-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 11-2: Maximum PCLK Frequency with FPM-DRAM . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 11-3: Example Frame Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Table 12-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 13-1: Power Save Mode Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 13-2: Pin States in Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 9
List of Figures
Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 4-1: Figure 5-1: Figure 5-2: Figure 5-3: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . . . 14 Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000) . . . . 15 Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030) . . 15 Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM . . . . . . . . . . . . . . . 16 System Block Diagram Showing Datapaths . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Pinout Diagram of F0A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pinout Diagram of F1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Pinout Diagram of F2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MC68K Bus 1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 MC68K Bus 2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Generic MPU Interface Synchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Generic MPU Interface Asynchronous Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 EDO-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 EDO-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 EDO-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7-10: EDO-DRAM CAS Before RAS Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 7-11: EDO-DRAM Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Figure 7-12: FPM-DRAM Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Figure 7-13: FPM-DRAM Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Figure 7-14: FPM-DRAM Read-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 7-16: FPM-DRAM CBR Self-Refresh Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 7-17: LCD Panel Power-On/Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 7-18: LCD Panel Suspend Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 7-19: Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 7-21: Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 7-23: Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 7-24: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 7-25: Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 7-27: Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 7-29: Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 7-30: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 7-31: Dual Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 10
Epson Research and Development Vancouver Design Center
Figure 7-33: Dual Color 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figure 7-34: Dual Color 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 7-35: Dual Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 7-36: Dual Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 7-37: 16-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 7-38: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 7-39: CRT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 7-40: CRT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 7-41: Generic Bus RAMDAC Read / Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 9-1: Display Buffer Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 10-3: Image Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 12-1: 1 Bit-Per-Pixel - 2-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . 122 Figure 12-2: 2 Bit-Per-Pixel - 4-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . . 123 Figure 12-3: 4 Bit-Per-Pixel - 16-Level Gray-Shade Mode Look-Up Table Architecture . . . . . . . . . . . 123 Figure 12-4: 1 Bit-Per-Pixel - 2-Level Color Look-Up Table Architecture . . . . . . . . . . . . . . . . . . 124 Figure 12-5: 2 Bit-Per-Pixel - 4-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . . 125 Figure 12-6: 4 Bit-Per-Pixel - 16-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . 126 Figure 12-7: 8 Bit-Per-Pixel - 256-Level Color Mode Look-Up Table Architecture . . . . . . . . . . . . . . 127 Figure 14-1: Mechanical Drawing QFP15-128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Figure 14-2: Mechanical Drawing TQFP15-128 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 14-3: Mechanical Drawing QFP20-144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 11
1 Introduction
1.1 Scope
This is the Functional Specification for the SED1354 Series Color Graphics LCD/CRT Controller Chip. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers.
1.2 Overview Description
The SED1354 is a low cost, low power color/monochrome LCD/CRT controller interfacing to a wide range of CPUs and LCDs. The SED1354 architecture is designed to meet the requirements of embedded markets such as Office Automation equipment, Mobile Communications devices and Hand-Held PCs where Windows CE may serve as a primary operating system. The SED1354 supports LCD interfaces with data widths up to 16 bits. Using Frame Rate Modulation (FRM), it can display 16 shades of gray on monochrome LCD panels, up to 4096 colors on passive color LCDs, and 64K colors on active matrix TFT LCD panels. CRT support is handled through the use of an external RAMDAC interface allowing simultaneous display of both the CRT and LCD panel. A 16-bit memory interface supports up to 2M bytes of FPM-DRAM or EDO-DRAM. Flexible operating voltages from 2.7V to 5.5V provide for very low power consumption.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 12
Epson Research and Development Vancouver Design Center
2 Features
2.1 Memory Interface
* 16-bit DRAM interface: * EDO-DRAM up to 40MHz data rate (80M bytes per second). * FPM-DRAM up to 25MHz data rate (50M bytes per second). * Memory size options: * 512K bytes using one 256Kx16 device. * 2M bytes using one 1Mx16 device. * A configuration register can be programmed to enhance performance by tailoring the memory control output timing to the DRAM device.
2.2 CPU Interface
* Supports the following interfaces: * 8/16-bit Hitachi SH-3 bus interface. * 16-bit interface to 16/32-bit Motorola MC68K microprocessors/microcontrollers. * Philips MIPS PR31500 / PR31700. * NEC MIPS VR4102. * 8/16-bit generic interface bus. * One-Stage write buffer for minimum wait-state CPU writes. * Registers are memory-mapped; M/R# pin selects between memory and register address space. * The complete 2M byte display buffer address space is directly and contiguously available through the 21-bit address bus.
2.3 Display Support
* 4/8-bit monochrome or 4/8/16-bit color passive LCD interface for single-panel, single-drive displays. * 8-bit monochrome or 8/16-bit color passive LCD interface for dual-panel, dual-drive displays. * Direct support for 9/12-bit TFT, 18/24-bit TFT are supported up to 64K color depth (16-bit data). * External RAMDAC support using the upper byte of the LCD data bus for the RAMDAC pixel data bus. * Simultaneous display of CRT and 4/8-bit passive panel or 9-bit TFT panel: * Normal mode for cases where LCD and CRT image sizes are identical. * Line-Doubling mode for simultaneous display of 240-line images on 240-line LCD and 480line CRT. * Even-Scan and interlace modes for simultaneous display of 480-line images on 240-line LCD and 480-line CRT.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 13
2.4 Display Modes
* 1/2/4/8/16 bit-per-pixel modes supported on LCD. * 1/2/4/8 bit-per-pixel modes supported on CRT. * Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 Look-Up Table is used to map 1/2/4 bit-per-pixel modes into these shades. * Up to 4096 colors on color passive LCD panels; three 16x4 Look-Up Tables are used to map 1/2/4/8 bit-per-pixel modes into these colors, 16 bit-per-pixel mode is mapped directly using the 4 most significant bits of the red, green and blue colors. * Up to 64K colors in 16 bit-per-pixel mode on TFT panels. * Split screen mode - allows two different images to be simultaneously displayed. * Virtual display mode - displays images larger than the panel size through the use of panning and scrolling. * Double buffering / multi-pages - for smooth animation and instantaneous screen update. * Fast-Update feature - accelerates screen update by allocating full display buffer bandwidth to CPU (see REG[23h] bit 7).
2.5 Clock Source
* Single clock input for both pixel and memory clocks. * Memory clock can be input clock or (input clock)/2 - this provides flexibility to use CPU bus clock as input clock. * Pixel clock can be memory clock, (memory clock)/2, (memory clock)/3 or (memory clock)/4.
2.6 Miscellaneous
* The memory data bus MD[15:0], is used to configure the chip at power-on. * Up to 12 General Purpose Input/Output pins are available: * GPIO0 is always available. * GPIO[3:1] are available if upper Memory Address pins are not required for DRAM support. * GPIO[11:4] are available if there is no external RAMDAC. * Suspend power save mode is initiated by hardware or software. * The SUSPEND# pin is used either as an input to initiate Suspend mode, or as a General Purpose Output that can be used to control the LCD backlight - its power-on polarity is selected by an MD configuration pin.
2.7 Package and Pin
Table 2-1: SED1354 Series Package list Name SED1354F0A SED1354F1A SED1354F2A Package QFP15 TQFP15 QFP20 Pin 128 128 144
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 14
Epson Research and Development Vancouver Design Center
3 Typical System Implementation Diagrams
Power Management SH-3 BUS
SUSPEND# A21 M/R#
Oscillator
CSn# A[20:0] D[15:0]
CS# AB[20:0] DB[15:0]
CLKI
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
WE1# BS# RD/WR# RD# WE0# WAIT#
4/8/16-bit LCD Display
WE1# BS# RD/WR# RD# WE0# WAIT#
SED1354
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR WE# RAS# BUSCLK RESET# LCAS# LCAS# UCAS# UCAS# CKIO RESET# MA[11:0] A[11:0] MD[15:0] D[15:0]
1Mx16 FPM/EDO-DRAM
Figure 3-1: Typical System Diagram - SH-3 Bus, 1Mx16 FPM/EDO-DRAM
SED1354 X19A-A-002-16
RAS#
WE#
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 15
.
Power Management MC68000 BUS
SUSPEND# A[23:21] FC0, FC1 Decoder M/R#
Oscillator
Decoder A[20:1] D[15:0]
CS# AB[20:1] DB[15:0]
CLKI
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
4/8/16-bit LCD Display
LDS# UDS# AS# R/W# DTACK#
AB0# WE1# BS# RD/WR# WAIT#
SED1354
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR WE# RAS# BUSCLK RESET# LCAS# LCAS# CLKI UCAS# UCAS# BCLK RESET# MA[11:0] A[11:0] MD[15:0] D[15:0]
1Mx16 FPM/EDO-DRAM
Figure 3-2: Typical System Diagram - MC68K Bus 1, 1Mx16 FPM/EDO-DRAM (16-Bit MC68000)
Power Management MC68030 BUS
A[31:21] FC0, FC1 Decoder M/R# SUSPEND#
Oscillator
Decoder A[20:0] D[31:16]
CS# AB[20:0] DB[15:0]
RAS#
WE#
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
DS# AS# R/W# SIZ1 SIZ0 DSACK1#
4/8/16-bit LCD Display
WE1# BS# RD/WR# RD# WE0# WAIT#
SED1354
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR MA[8:0] WE# RAS# BUSCLK RESET# LCAS# LCAS# UCAS# UCAS# BCLK RESET# MD[15:0] D[15:0]
256Kx16 FPM/EDO-DRAM
Figure 3-3: Typical System Diagram - MC68K Bus 2, 256Kx16 FPM/EDO-DRAM (32-Bit MC68030)
Hardware Functional Specification Issue Date: 99/05/18
A[8:0]
RAS#
WE#
SED1354 X19A-A-002-16
Page 16
Epson Research and Development Vancouver Design Center
.
Power Management GENERIC BUS
SUSPEND# A21 M/R#
Oscillator
CSn# A[20:0] D[15:0]
CS# AB[20:0] DB[15:0]
CLKI
FPDAT[15:8] FPDAT[7:0] FPSHIFT
UD[7:0] LD[7:0] FPSHIFT
4/8/16-bit LCD Display
WE0# WE1# RD0# RD1# WAIT#
WE0# WE1# RD# RD/WR# WAIT#
SED1354
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
LCDPWR LCAS# LCAS# WE# RAS# BUSCLK RESET# UCAS# UCAS# BCLK RESET# MA[11:0] A[11:0] MD[15:0] D[15:0]
1Mx16 FPM/EDO-DRAM
Figure 3-4: Typical System Diagram - Generic Bus, 1Mx16 FPM/EDO-DRAM
SED1354 X19A-A-002-16
RAS#
WE#
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 17
4 Block Description
4.1 Functional Block Diagram
16-bit FPM/EDO DRAM
Register
Memory Controller
Power Save
Clocks CPU R/W Host CPU / MPU I/F Display FIFO Look-Up Table LCD I/F
LCD DAC Data
DAC Control CRTC Bus Clock Memory Clock Pixel Clock
Figure 4-1: System Block Diagram Showing Datapaths
4.2 Functional Block Descriptions 4.2.1 Host Interface
The Host Interface block provides the means for the CPU/MPU to communicate with the display buffer and internal registers, via one of the supported bus interfaces.
4.2.2 Memory Controller
The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPMDRAM or EDO-DRAM).
4.2.3 Display FIFO
The Display FIFO block fetches display data from the Memory Controller for display refresh.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 18
Epson Research and Development Vancouver Design Center
4.2.4 Look-Up Table
The Look-Up Table block contains three 16x4 Look-Up Tables, one for each primary color. In monochrome mode only one of these Look-Up Tables is selected and used.
4.2.5 LCD Interface
The LCD Interface block performs frame rate modulation for passive LCD panels. It also generates the correct data format and timing control signals for various LCD and TFT panels.
4.2.6 Power Save
The Power Save block contains the power save mode circuitry.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 19
5 Pin Out
5.1 Pinout Diagram for SED1354F0A
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 FPDAT3 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT2 FPDAT1 FPDAT0 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD0 MD14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
COREVDD DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC VSS CLKI SUSPEND# TESTEN BUSCLK VSS IOVDD AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 RD/WR# RESET# WAIT# IOVDD GPIO0 WE0# WE1# DB11 DB10 DB15 DB14 DB13 DB12 M/R#
MD1 MD13 MD2 MD12 MD3 MD11 MD4 MD10 MD5 MD9 MD6 MD8 MD7 VSS LCAS# UCAS# WE# RAS# IOVDD MA9 MA11 MA8 MA10 MA7 MA0 MA6 MA1 MA5 MA2 MA4 MA3 COREVDD
SED1354F0A
VSS
VSS
AB1 2
BS#
DB9
DB6 DB7
DB8
DB5
DB4
DB3
DB2
DB1
DB0
Package type: 128 pin surface mount QFP15
Hardware Functional Specification Issue Date: 99/05/18
AB2 1
AB0 3
CS# 4
RD# 6 7
5
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5-1: Pinout Diagram of F0A
SED1354 X19A-A-002-16
Page 20
Epson Research and Development Vancouver Design Center
5.2 Pinout Diagram for SED1354F1A
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 FPDAT3 VSS FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT2 FPDAT1 FPDAT0 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD0 MD14 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
COREVDD DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC VSS CLKI SUSPEND# TESTEN BUSCLK VSS IOVDD AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 RD/WR# RESET# WAIT# IOVDD GPIO0 WE0# WE1# DB11 DB10 DB15 DB14 DB13 DB12 M/R#
MD1 MD13 MD2 MD12 MD3 MD11 MD4 MD10 MD5 MD9 MD6 MD8 MD7 VSS LCAS# UCAS# WE# RAS# IOVDD MA9 MA11 MA8 MA10 MA7 MA0 MA6 MA1 MA5 MA2 MA4 MA3 COREVDD
SED1354F1A
VSS
VSS
AB1 2
BS#
DB9
DB6 DB7
DB8
DB5
DB4
DB3
DB2
DB1
DB0
Package type: 128 pin surface mount TQFP15
AB2 1
AB0 3
CS# 4
RD# 6 7
5
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 5-2: Pinout Diagram of F1A
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 21
5.3 Pinout Diagram for SED1354F2A
108107106105104103 10210110099 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
NC NC FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 FPDAT8 VSS DACCLK BLANK# DACRD# IOVDD FPDAT7 FPDAT6 FPDAT5 FPDAT1 FPDAT0 MD0 NC NC VSS FPDAT15 FPDAT14 FPDAT4 FPDAT2 VSS FPSHIFT DRDY LCDPWR FPLINE FPFRAME VSS MD15 MD14 FPDAT3
109 NC 110
NC
111 COREVDD 112 113 114
DACP0 DACWR# DACRS0 HRTC VRTC
NC NC MD1 MD13 MD2 MD12 MD3 MD11 MD4 MD10 MD5 MD9 MD6 MD8 MD7 VSS LCAS# UCAS# WE# RAS# IOVDD MA9 MA11 MA8 MA10 MA7 MA0 MA6 MA1 MA5 MA2 MA4 MA3 COREVDD NC NC
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
115 DACRS1 116 117 118 VSS 119 120 121
CLKI SUSPEND# TESTEN
122 BUSCLK 123 124 125
VSS IOVDD AB20
126 AB19 127 128
AB18 AB17
SED1354F2A
129 AB16 130 131
AB15 AB14
132 AB13 133 AB12 134
AB11 AB10 AB9 AB7 AB5
135 136
137 AB8 138 139 AB6 140 141 AB4 142 AB3 143 NC 144 NC
RD/WR# RESET# IOVDD WAIT# GPIO0 WE0# WE1# DB15 DB14 DB13 DB12 DB11 DB10 M/R#
RD#
VSS
NC VSS
CS#
DB6 DB7
DB8
DB5
DB4
DB3
DB2
DB1
DB0
DB9
AB1
AB0
BS#
AB2
Package type: 144 pin surface mount QFP20
Hardware Functional Specification Issue Date: 99/05/18
NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
NC
NC
Figure 5-3: Pinout Diagram of F2A
SED1354 X19A-A-002-16
Page 22
Epson Research and Development Vancouver Design Center
5.4 Pin Description
Key:
I O IO P C CD CS COx TSx TSxD CNx = = = = = = = = = = = Input Output Bi-Directional (Input/Output) Power pin CMOS level input CMOS level input with pull-down resistor (typical values of 100K/180K at 5V/3.3V respectively) CMOS level Schmitt input CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) Tri-state CMOS output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) Tri-state CMOS output driver with pull-down resistor (typical values of 100K/180K at 5V/3.3V respectively), x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA) CMOS low-noise output driver, x denotes driver type (1=3/-1.5mA, 2=6/-3mA, 3=12/-6mA)
5.4.1 Host Interface
Table 5-1: Host Interface Pin Descriptions Pin Name Type Pin # F0A F2A F1A Driver Reset = 0 Value Description This pin has multiple functions. * * * * For SH-3 mode, this pin inputs system address bit 0 (A0). For MC68K Bus 1, this pin inputs the lower data strobe (LDS#). For MC68K Bus 2, this pin inputs system address bit 0 (A0). For Generic Bus, this pin inputs system address bit 0 (A0).
AB0
I
3
5
CS
Hi-Z
See Table 5-9: "Host Bus Interface Pin Mapping," on page 32 for summary. AB[20:1] I 111-128 125-142 C 1, 2 3,4 Hi-Z System address bus bits [20:1]. System data bus. Unused data pins should be connected to IO VDD. * For SH-3 mode, these pins are connected to D[15:0]. * For MC68K Bus 1, these pins are connected to D[15:0]. * For MC68K Bus 2, these pins are connected to D[31:16] for 32bit devices (e.g. MC68030) or D[15:0] for 16-bit devices (e.g. MC68340). * For Generic Bus, these pins are connected to D[15:0]. See Table 5-9: "Host Bus Interface Pin Mapping," on page 32 for summary.
DB[15:0]
IO
16-31
18-33
C/TS2
Hi-Z
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 23
Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # F0A F2A F1A Driver Reset = 0 Value Description This pin has multiple functions. * For SH-3 mode, this pin inputs the write enable signal for the upper data byte (WE1#). * For MC68K Bus 1, this pin inputs the upper data strobe (UDS#). * For MC68K Bus 2, this pin inputs the data strobe (DS#). * For Generic Bus, this pin inputs the write enable signal for the upper data byte (WE1#). See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. This input pin is used to select between the memory and register address spaces of the SED1354. M/R# is set high to access the memory and low to access the registers. See Section 8.1, "Register Mapping" on page 90. See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. CS# BUSCLK I I 4 108 6 122 C C Hi-Z Hi-Z Chip select input. See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. System bus clock. See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. This pin has multiple functions. * * * * For SH-3 mode, this pin inputs the bus start signal (BS#). For MC68K Bus 1, this pin inputs the address strobe (AS#). For MC68K Bus 2, this pin inputs the address strobe (AS#). For Generic Bus, this pin must be tied to IO V DD.
WE1#
I
9
11
CS
Hi-Z
M/R#
I
5
7
C
Hi-Z
BS#
I
6
8
CS
Hi-Z
See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. This pin has multiple functions. * For SH-3 mode, this pin inputs the RD/WR# signal. The SED1354 needs this signal for early decode of the bus cycle. * For MC68K Bus 1, this pin inputs the R/W# signal. * For MC68K Bus 2, this pin inputs the R/W# signal. * For Generic Bus, this pin inputs the read command for the upper data byte (RD1#). See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. This pin has multiple functions. * * * * For SH-3 mode, this pin inputs the read signal (RD#). For MC68K Bus 1, this pin must be tied to IO VDD. For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1). For Generic Bus, this pin inputs the read command for the lower data byte (RD0#).
RD/WR#
I
10
12
CS
Hi-Z
RD#
I
7
9
CS
Hi-Z
See Table 5-9: "Host Bus Interface Pin Mapping," on page 32.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 24
Epson Research and Development Vancouver Design Center
Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # F0A F2A F1A Driver Reset = 0 Value Description This pin has multiple functions. * For SH-3 mode, this pin inputs the write enable signal for the lower data byte (WE0#). * For MC68K Bus 1, this pin must be tied to IO V DD. * For MC68K Bus 2, this pin inputs the bus size bit 0 (SIZ0). * For Generic Bus, this pin inputs the write enable signal for the lower data byte (WE0#). See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. The active polarity of the WAIT# output is configurable on the rising edge of RESET# - see Section 5.5, "Summary of Configuration Options" on page 31. This pin has multiple functions. * For SH-3 mode, this pin outputs the wait request signal (WAIT#); MD5 must be pulled low during reset by the internal pull-down resistor. * For MC68K Bus 1, this pin outputs the data transfer acknowledge signal (DTACK#); MD5 must be pulled high during reset by an external pull-up resistor. * For MC68K Bus 2, this pin outputs the data transfer and size acknowledge bit 1 (DSACK1#); MD5 must be pulled high during reset by an external pull-up resistor. * For Generic Bus, this pin outputs the wait signal (WAIT#); MD5 must be pulled low during reset by the internal pull-down resistor. See Table 5-9: "Host Bus Interface Pin Mapping," on page 32. RESET# I 11 13 CS Input 0 Active low input to clear all internal registers and to force all signals to their inactive states.
WE0#
I
8
10
CS
Hi-Z
WAIT#
O
13
15
TS2
Hi-Z
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 25
5.4.2 Memory Interface
Table 5-2: Memory Interface Pin Descriptions Pin # Pin Name Type F0A F1A F2A Driver Reset = 0 Value Description This pin has multiple functions. * For dual CAS# DRAM, this is the column address strobe for the lower byte (LCAS#). * For single CAS# DRAM, this is the column address strobe (CAS#). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For dual CAS# DRAM, this is the column address strobe for the upper byte (UCAS#). * For single CAS# DRAM, this is the write enable signal for the upper byte (UWE#). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For dual CAS# DRAM, this is the write enable signal (WE#). * For single CAS# DRAM, this is the write enable signal for the lower byte (LWE#). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. RAS# O 47 67, 65, 63, 61, 59, 57, 55, 53, 52, 54, 56, 58, 60, 62, 64, 66 53 76, 70, 68, 66, 64, 62, 60, 58, 59, 61, 63, 65, 67, 69, 75, 77 CO1 Output 1 Row address strobe. These pins have multiple functions. * Bi-directional memory data bus. * During reset, these pins are inputs and their states at the rising edge of RESET# are used to configure the chip. Hi-Z CD2/TS1 Internal pull-down resistors (typical values of (pulled 0) 100K/100K/120K at 5.0V/3.3V/3.0V respectively) pull the reset states to 0. External pull-up resistors can be used to pull the reset states to 1. See Section 5.5, "Summary of Configuration Options" on page 31.
LCAS#
O
50
56
CO1
Output 1
UCAS#
O
49
55
CO1
Output 1
WE#
O
48
54
CO1
Output 1
MD[15:0] IO
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 26
Epson Research and Development Vancouver Design Center
Table 5-2: Memory Interface Pin Descriptions (Continued) Pin # Pin Name Type F0A F1A 43, 41, 39, 37, 35, 34, 36, 38, 40 F2A 46, 44, 42, 40, 41, 43, 45, 47, 49 Driver Reset = 0 Value Description
MA[8:0]
O
CO1
Output 0
Multiplexed memory address.
This pin has multiple functions. * For 2M byte DRAM, this is memory address bit 9 (MA9). * For asymmetrical 512K byte DRAM, this is memory address bit 9 (MA9). Hi-Z / Output 01 * For symmetrical 512K byte DRAM, this pin can be used as general purpose IO (GPIO3). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For asymmetrical 2M byte DRAM, this is memory address bit 10 (MA10). Hi-Z / * For symmetrical 2M byte DRAM and all 512K byte DRAM, Output 01 this pin can be used as general purpose IO (GPIO1). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. This pin has multiple functions. * For asymmetrical 2M byte DRAM, this is memory address bit 11 (MA11). Hi-Z / 1 * For symmetrical 2M byte DRAM and all 512K byte DRAM, Output 0 this pin can be used as general purpose IO (GPIO2). See Table 5-10: "Memory Interface Pin Mapping," on page 32 for summary. 1 When configured as IO pins.
MA9
IO
45
51
C/TS1
MA10
IO
42
48
C/TS1
MA11
IO
44
50
C/TS1
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 27
5.4.3 LCD Interface
Table 5-3: LCD Interface Pin Descriptions Pin # Pin Name Type F0A F!A Driver F2A Reset = 0 Value Output 0 Panel Data These pins have multiple functions. FPDAT[15:9] O 95-89 105-99 CN3 * Panel Data for 16-bit panels. Output 0 * Pixel Data for external RAMDAC support. See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. FPFRAME FPLINE FPSHIFT O O O 69 70 73 79 80 83 CN3 CN3 CN3 Output 0 Frame Pulse Output 0 Line Pulse Output 0 Shift Clock Pulse LCD power control output. The active polarity of this output is selected by the state of MD10 at the rising edge of RESET# - see Section 5.5, "Summary of Configuration Options" on page 31. This output is controlled by the power save mode circuitry see Section 13, "Power Save Modes" on page 128 for details. This pin has multiple functions which are automatically selected depending on panel type used. * For TFT panels, this is the display enable output (DRDY). * For passive LCDs with Format 1 interfaces, this is the Output 0 2nd Shift Clock (FPSHIFT2). * For all other LCD panels, this is the LCD backplane bias signal (MOD). See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33 and REG[02h] for details. 1 Output may be 1 or 0. Description
FPDAT[8:0]
O
88, 82-75 98, 92-85 CN3
LCDPWR
O
71
81
CO1
Output1
DRDY
O
72
82
CN3
5.4.4 Clock Input
Table 5-4: Clock Input Pin Description Pin # Pin Name Type F0A F1A 105 F2A Driver Reset = 0 Value Description Input clock for the internal pixel clock (PCLK) and memory clock (MCLK). PCLK and MCLK are derived from CLKI - see REG[19h] for details.
CLKI
I
119
C
Hi-Z
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 28
Epson Research and Development Vancouver Design Center
5.4.5 CRT and External RAMDAC Interface
Table 5-5: CRT and RAMDAC Interface Pin Descriptions Pin # Pin Name Type F0A F1A F2A Driver Reset = 0 Value Description This pin has multiple functions. DACRD# IO 84 94 C/TS1 * Read signal for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO4). Output 11 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACWR# IO 99 113 C/TS1 * Write signal for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO7). Output 11 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACRS1 IO 101 115 C/TS1 * Register Select bit 1 for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO9). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACRS0 IO 100 114 C/TS1 * Register Select bit 0 for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO8). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. DACP0 IO 98 112 C/CN3 * Pixel Data bit 0 for external RAMDAC support. Hi-Z / * General Purpose IO (GPIO6). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 29
Table 5-5: CRT and RAMDAC Interface Pin Descriptions (Continued) Pin # Pin Name Type F0A F1A F2A Driver Reset = 0 Value Description This pin has multiple functions. HRTC IO 102 116 C/CN3 * Horizontal Retrace signal for CRT. Hi-Z / 1 * General Purpose IO (GPIO10). Output 0 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. VRTC IO 103 117 C/CN3 * Vertical Retrace signal for CRT. Hi-Z / * General Purpose IO (GPIO11). Output 01 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. This pin has multiple functions. BLANK# IO 85 95 C/CN3 * Blanking signal for DAC. Hi-Z / 1 * General Purpose IO (GPIO5). Output 0 See Table 5-11: "LCD, CRT, RAMDAC Interface Pin Mapping," on page 33. Output 0 Pixel Clock for RAMDAC.
DACCLK 1
O
86
96
C/CN3
When configured as IO pins
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 30
Epson Research and Development Vancouver Design Center
5.4.6 Miscellaneous
Table 5-6: Miscellaneous Pin Descriptions Pin # Pin Name Type F0A F1A F2A Driver Reset = 0 Value Description This pin has multiple functions. * When MD9 = 0 at rising edge of RESET#, this pin is an active-low input used to place the SED1354 into suspend mode; see Section 13, "Power Save Modes" on page 128 for details. * When MD[10:9] = 01 at rising edge of RESET#, this pin is an output with a reset state of 0. Its state is controlled by REG[21h] bit 7. * When MD[10:9] = 11 at rising edge of RESET#, this pin is an output with a reset state of 1. Its state is controlled by REG[21h] bit 7. General Purpose IO pin 0. Test Enable. This in should be connected to VSS for normal operation.
SUSPEND# IO
106
120
CS/TS1
Hi-Z / Output1
GPIO0 TSTEN
IO I
12 107
14 121
C/TS1 CD
Hi-Z Hi-Z (pulled 0)
NC
-
-
1, 2, 3538, 7174, 107- 110, 143, 144
-
No connect
1
When configured as IO pin. Output may be 1 or 0.
5.4.7 Power Supply
Table 5-7: Power Supply Pin Descriptions Pin # Pin Name COREVDD IOVDD P P Type F0A F1A 33, 97 14, 46, 83, 110 15, 32, 51, 68, 74, 87, 96, 104, 109 F2A 39, 111 16, 52, 93, 124 17, 34, 57, 78, 84, 97, 106, 118, 123, P P Driver Core VDD IO VDD Description
VSS
P
P
Common VSS
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 31
5.5 Summary of Configuration Options
Table 5-8: Summary of Power On / Reset Options Pin Name MD0 value on this pin at rising edge of RESET# is used to configure: 1 8-bit host bus interface 16-bit host bus interface 0 (1/0)
MD[3:1]
Select host bus interface: 000 = SH-3 bus interface 001 = MC68K bus 1 (e.g. MC68000) 010 = MC68K bus 2 (e.g. MC68030) 011 = Generic bus interface (e.g. Philips MIPS PR31500/PR31700; NEC MIPS VR4102) 1XX = reserved Little Endian WAIT# is active high (1 = insert wait state) Memory Address/GPIO configuration: 00 = symmetrical 256Kx16 DRAM. 01 = symmetrical 1Mx16 DRAM. 10 = asymmetrical 256Kx16 DRAM. 11 = asymmetrical 1Mx16 DRAM. Big Endian WAIT# is active low (0 = insert wait state) = GPIO[2:1] and GPIO3. = GPIO[2:1]. = GPIO[2:1].
MD4 MD5
MD[7:6]
MA[8:0] = DRAM address. MA[11:9] MA[9:0] = DRAM address. MA[11:10] MA[9:0] = DRAM address. MA[11:10] MA[11:0] = DRAM address.
MD8 MD9 MD10 MD[15:11]
Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as General Purpose IO (GPIO[11:4]). SUSPEND# pin configured as GPO output. Active low LCDPWR or GPO polarities. Not used.
Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as DAC and CRT outputs. SUSPEND# pin configured as SUSPEND# input. Active high LCDPWR or GPO polarities.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 32
Epson Research and Development Vancouver Design Center
5.6 Multiple Function Pin Mapping
Table 5-9: Host Bus Interface Pin Mapping SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# SH-3 A[20:1] A0 D[15:0] WE1# External Decode CSn# CKIO BS# RD/WR# RD# WE0# WAIT# RESET# MC68K Bus 1 A[20:1] LDS# D[15:0] UDS# External Decode External Decode CLK AS# R/W# Connect to IO VDD Connect to IO VDD DTACK# RESET# MC68K Bus 2 A[20:1] A0 D[31:16] DS# External Decode External Decode CLK AS# R/W# SIZ1 SIZ0 DSACK1# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
Table 5-10: Memory Interface Pin Mapping SED1354 Pin Names MD[15:0] MA[8:0] MA9 MA10 MA11 UCAS# LCAS# WE# RAS# UCAS# LCAS# WE# UWE# CAS# LWE# GPIO31 GPIO11 GPIO21 UCAS# LCAS# WE# UWE# CAS# LWE# RAS# UCAS# LCAS# WE# UWE# CAS# LWE# UCAS# LCAS# WE# FPM/EDO-DRAM Sym 256Kx16 2-CAS# 2-WE# Asym 256Kx16 2-CAS# 2-WE# A[8:0] A9 A10 A11 UWE# CAS# LWE# DQ[15:0] Sym 1Mx16 2-CAS# 2-WE# Asym 1Mx16 2-CAS# 2-WE#
Note 1. All GPIO pins default to input on reset, and unless programmed otherwise should be connected to either VSS or IO VDD if not used.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 33
Table 5-11: LCD, CRT, RAMDAC Interface Pin Mapping
Monochrome Passive Panel Single 4-bit FPFRAME FPLINE FPSHIFT DRDY FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 DACRD# BLANK# DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC DACCLK driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 MOD LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 D0 D1 D2 D3 D4 D5 D6 D7 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 8-bit Dual 8-bit Single 4-bit Color Passive Panel Single
Format 1
SED1354 Pin Names
Single
Format 2
Color TFT Panel Dual 8-bit 16-bit 9-bit 12-bit 18-bit1
CRT
8-bit
8-bit FPFRAME FPLINE FPSHIFT
Note2 Note2 Note2 MOD DRDY LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 R2 R1 R0 G2 G1 G0 B2 B1 B0 driven 0 driven 0 R3 R2 R1 G3 G2 G1 B3 B2 B1 R0 G0 R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 G2 G1 G0 B2 B1 Note 2 Note2 Note2 Note2 Note2 Note2 Note2 Note2 Note2 Note2 DACP7 DACP6 DACP5 DACP4 DACP3 DACP2 DACP1 DACRD# BLANK# DACP0 DACWR# DACRS0 DACRS1 HRTC VRTC DACCLK LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3
FPSHIFT2 D0 D1 D2 D3 D4 D5 D6 D7
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO43 GPIO53 GPIO63 GPIO73 GPIO83 GPIO9
3
driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 B0 driven 0 driven 0
GPIO103 GPIO113 driven 0
Note 1. Although 18-bit TFT panels are supported only 16 data bits (64K colors) are available - R0 and B0 are not used. 2. If no LCD is active these pins are driven low. 3. All GPIO pins default to input on reset, and unless programmed otherwise should be connected to either VSS or IO VDD if not used.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 34
Epson Research and Development Vancouver Design Center
6 D.C. Characteristics
Table 6-1: Absolute Maximum Ratings Symbol Core VDD IO VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time VSS - 0.3 to 4.6 VSS - 0.3 to 6.0 VSS - 0.3 to IO VDD + 0.5 VSS - 0.3 to IO VDD + 0.5 -65 to 150 260 for 10 sec. max at lead Rating V V V V C C Units
Table 6-2: Recommended Operating Conditions Symbol Core VDD IO VDD VIN TOPR Parameter Supply Voltage Supply Voltage Input Voltage Operating Temperature Condition VSS = 0 V VSS = 0 V 2.7 2.7 VSS -40 25 Min Typ 3.0/3.3 3.0/3.3/5.0 3.6 5.5 IO VDD 85 Max V V V C Units
Table 6-3: Input Specifications Symbol VIL Parameter Low Level Input Voltage CMOS inputs High Level Input Voltage CMOS inputs Positive-Going Threshold CMOS Schmitt inputs Negative-Going Threshold CMOS Schmitt inputs Condition IO VDD = 3.0 3.3 5.0 3.0 3.3 5.0 3.0 3.3 5.0 3.0 3.3 5.0 1.9 2.0 3.5 1.0 1.1 2.0 0.5 0.6 0.8 -1 2.3 2.4 4.0 1.7 1.8 3.1 1 10 VIN = VDD = 3.0 = 3.3 = 5.0 60 50 50 120 100 100 300 300 300 Min Typ 0.8 0.8 1.0 Max V V V V V V V V V V V V A pF k k k Units
IO VDD =
VIH
IO VDD =
VT+
IO VDD =
VT-
IIZ CIN HRPD
Input Leakage Current Input Pin Capacitance Pull-down Resistance
VDD = Max VIH = IO VDD VIL = VSS
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 35
Table 6-4: Output Specifications Symbol Parameter Low Level Output Voltage Type 1 - TS1, CO1, TS1D Type 2 - TS2, CO2 Type 3 - TS3, CO3 High Level Output Voltage Type 1 - TS1, CO1, TS1D Type 2 - TS2, CO2 Type 3 - TS3, CO3 Output Leakage Current Output Pin Capacitance Bidirectional Pin Capacitance Condition IOL = 3mA IOL = 6mA IOL = 12mA IOL = -1.5 mA IOL = -3 mA IOL = -6 mA IO VDD = Max VOH = VDD VOL = VSS Min Typ Max Units
VOL
0.4
V
VOH
IO VDD - 0.4
V
IOZ COUT CBID
-1
1 10 10
A pF pF
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 36
Epson Research and Development Vancouver Design Center
7 A.C. Characteristics
Conditions: IO VDD = 2.7V to 5.5V unless otherwise specified TA = -40 C to 85 C Trise and Tfall for all inputs must be 5 nsec (10% ~ 90%) CL = 50pF (Bus / MPU Interface) CL = 100pF (LCD Panel Interface) CL = 10pF (Display Buffer Interface) CL = 10pF (CRT / DAC Interface)
7.1 CPU Interface Timing 7.1.1 SH-3 Interface Timing
t1 CKIO t4 A[20:0], M/R# RD/WR# t6 BS# t8 CSn# t9 WEn# RD# t11 WAIT# t13 D[15:0](write) t15 D[15:0](read) t16 t14 t12 t10 t12 t7 t5 t2 t3
Figure 7-1: SH-3 Interface Timing
Note The SH-3 Wait State Control Register for the area in which the SED1354 resides must be set to a non-zero value.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 37
Table 7-1: SH-3 Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9
2
Parameter Clock period Clock pulse width high Clock pulse width low A[20:0], M/R#, RD/WR# setup to CKIO A[20:0], M/R#, RD/WR# hold from CS# BS# setup BS# hold CSn# setup Falling edge RD# to D[15:0] driven Rising edge CSn# to WAIT# tri-state Falling edge CSn# to WAIT# driven CKIO to WAIT# delay D[15:0] setup to first CKIO after BS# (write cycle) D[15:0] hold (write cycle) D[15:0] valid to WAIT# rising edge (read cycle) Rising edge RD# to D[15:0] tri-state (read cycle)
Min 25 5 5 4 0 3 0 0 3 0 1 3 0 0 0 2
Max
Units ns ns ns ns ns ns ns ns ns
t10 t111 t12 t13 t14 t15 t16
4 11 15
ns ns ns ns ns ns
9
ns
1.
If the SED1354 host interface is disabled, the timing for WAIT# driven is relative to the falling edge of CSn# or the first positive edge of CKIO after A[20:0] and M/R# become valid, whichever occurs later. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD# or the first positive edge of CKIO after A[20:0] and M/R# become valid, whichever occurs later.
2.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 38
Epson Research and Development Vancouver Design Center
7.1.2 MC68K Bus 1 Interface Timing (e.g. MC68000)
t1 CLK t4 A[20:1] M/R# t6 CS# t16 AS# t5 t2 t3
UDS# LDS# t7 R/W# t9 DTACK# t11 D[15:0](write) t13 D[15:0](read) t14 t15 t12 t10 t8
Figure 7-2: MC68K Bus 1 Interface Timing
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 39
Table 7-2: MC68K Bus 1 Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9
1
Parameter Clock period Clock pulse width high Clock pulse width low A[20:1], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 A[20:1], M/R# hold from AS# CS# hold from AS# R/W# setup to before to either UDS#=0 or LDS# = 0 R/W# hold from AS# AS# = 0 and CS# = 0 to DTACK# driven high AS# high to DTACK# high impedance D[15:0] valid to second CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 (write cycle) D[15:0] hold from falling edge of DTACK# (write cycle) Falling edge of UDS#=0 or LDS# = 0 to D[15:0] driven (read cycle) D[15:0] valid to DTACK# falling edge (read cycle) UDS# and LDS# high to D[15:0] invalid/high impedance (read cycle) AS# high setup to CLK
Min 30 5 5 4 0 0 5 0 1 1 0 0 3 0 2 3
Max
Units ns ns ns ns ns ns ns ns ns
t10 t11 t12 t132 t14 t15 t16
5
ns ns ns ns ns
11
ns ns
1.
If the SED1354 host interface is disabled, the timing for DTACK# driven high is relative to the falling edge of AS# or the first positive edge of CLK after A[20:1] and M/R# become valid, whichever occurs later. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# become valid, whichever occurs later.
2.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 40
Epson Research and Development Vancouver Design Center
7.1.3 MC68K Bus 2 Interface Timing (e.g. MC68030)
t1 CLK t4 A[20:0] SIZ[1:0] M/R# t6 CS# t16 AS# t5 t2 t3
DS# t7 R/W# t9 DSACK1# t11 D[31:16](write) t13 D[31:16](read) t14 t15 t12 t10 t8
Figure 7-3: MC68K Bus 2 Interface Timing
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 41
Table 7-3: MC68K Bus 2 Interface Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9
1
Parameter Clock period Clock pulse width high Clock pulse width low A[20:0], SIZ[1:0], M/R# setup to first CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 A[20:0], SIZ[1:0], M/R# hold from AS# CS# hold from AS# R/W# setup to DS# R/W# hold from AS# AS# = 0 and CS# = 0 to DSACK1# driven high AS# high to DSACK1# high impedance D[31:16] valid to second CLK where CS# = 0 AS# = 0, and either UDS#=0 or LDS# = 0 (write cycle) D[31:16] hold from falling edge of DSACK1# (write cycle) Falling edge of UDS# = 0 or LDS# = 0 to D[31:16] driven (read cycle) D[31:16] valid to DSACK1# falling edge (read cycle) UDS# and LDS# high to D[31:16] invalid/high impedance (read cycle) AS# high setup to CLK
Min 30 5 5 4 0 0 5 0 1 1 0 0 3 0 2 3
Max
Units ns ns ns ns ns ns ns ns ns
t10 t11 t12 t132 t14 t15 t16
5
ns ns ns ns ns
11
ns ns
1.
If the SED1354 host interface is disabled, the timing for DSACK1# driven high is relative to the falling edge of AS# or the first positive edge of CLK after A[20:0] and M/R# become valid, whichever occurs later. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of UDS#/LDS# or the first positive edge of CLK after A[20:1] and M/R# becomes valid, whichever occurs later.
2.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 42
Epson Research and Development Vancouver Design Center
7.1.4 Generic MPU Interface Synchronous Timing
TBCLK BCLK t1 A[20:0] M/R# t1 CS# t3 t1 RD0#,RD1# WE0#,WE1# t4 Hi-Z WAIT# t7 Hi-Z D[15:0](write) t9 Hi-Z D[15:0](read) Valid t10 Valid t11 Hi-Z t8 Hi-Z t5 t2 t1 t2 t2 t2 Valid t1 t2 t1 t2
t6 Hi-Z
Figure 7-4: Generic MPU Interface Synchronous Timing
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 43
Table 7-4: Generic MPU Interface Synchronous Timing Symbol TBCLK t1 t2 t3 t41 t5 t6 t7 t8 t92 t10 t11 Bus clock period A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# hold time A[20:0], M/R#, CS#, RD0#,RD1#,WE0#,WE1# setup time RD0#,RD1#,WE0#,WE1# high to A[20:0], M/R# invalid and CS# high RD0#,RD1#,WE0#,WE1# low and CS# low to WAIT# driven low BCLK to WAIT# high RD0#,RD1#,WE0#,WE1# high to WAIT# high impedance D[15:0] valid to second BCLK where RD0#,RD1#,WE0#,WE1# low and CS# low (write cycle) D[15:0] hold from WE0#, WE1# high (write cycle) RD0#,RD1# low to D[15:0] driven (read cycle) D[15:0] valid to WAIT# high (read cycle) RD0#, RD1# high to D[15:0] high impedance (read cycle) Parameter Min 25 1 5 0 1 0 1 5 0 3 0 2 10 15 7 15 6 Max Units ns ns ns ns ns ns ns ns ns ns
1.
If the SED1354 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# and RD0#, RD1#, WE0#, WE1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.
2.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 44
Epson Research and Development Vancouver Design Center
7.1.5 Generic MPU Interface Asynchronous Timing
TBCLK BCLK
A[20:0] M/R# t1 CS# t2 RD0#,RD1# WE0#,WE1#
Valid
t3
Hi-Z WAIT#
t4
t5 Hi-Z t7 Valid Hi-Z t10 Valid Hi-Z
t6 D[15:0](write) Hi-Z t8 D[15:0](read) Hi-Z t9
Figure 7-5: Generic MPU Interface Asynchronous Timing
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 45
Table 7-5: Generic MPU Interface Asynchronous Timing Symbol TBCLK t1 t2 t3 t41 t5 t6 t7 t82 t9 t10 Bus clock period RD0#, RD1#, WE0#, WE1# low to CS# low A[20:0], M/R# valid to RD0#, RD1#, WE0#, WE1# low RD0#, RD1#, WE0#, WE1# high to A[20:0], CS#, M/R# invalid and CS# high CS# low to WAIT# driven low RD0#, RD1#, WE0#, WE1# high to WAIT# high impedance WE0#, WE1# low to D[15:0] valid (write cycle) D[15:0] hold from WE0#, WE1# high (write cycle) RD0#, RD1# low to D[15:0] driven (read cycle) D[15:0] valid to WAIT# high (read cycle) RD0#, RD1# high to D[15:0] high impedance (read cycle) 0 3 0 2 10 15 Parameter Min 25 4 0 0 1 1 7 6 20 Max Units ns ns ns ns ns ns ns ns ns
1.
If the SED1354 host interface is disabled, the timing for WAIT# driven low is relative to the falling edge of CS# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later. If the SED1354 host interface is disabled, the timing for D[15:0] driven is relative to the falling edge of RD0#, RD1# or the first positive edge of BCLK after A[20:0] and M/R# become valid, whichever occurs later.
2.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 46
Epson Research and Development Vancouver Design Center
7.2 Clock Input Requirements
Clock Input Waveform
t PWH t PWL
V IH VIL
TCLKI
Figure 7-6: Clock Input Requirements Table 7-6: Clock Input Requirements Symbol TCLKI TPCLK TMCLK tPWH tPWL Parameter Input Clock Period (CLKI) Pixel Clock Period (PCLK) not shown Memory Clock Period (MCLK) not shown Input Clock Pulse Width High (CLKI) Input Clock Pulse Width Low (CLKI) Min 12.5 25 25 45% 45% Typ Max Units ns ns ns TCLKI TCLKI
55% 55%
Note When CLKI is more than 40MHz, REG[19h] bit 2 must be set to 1 (MCLK = CLKI/2). There is no minimum frequency for CLKI.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 47
7.3 Memory Interface Timing 7.3.1 EDO-DRAM Read Timing
t1
Memory Clock
t2 t3 t4 t5 t6 t7 t8 t9
MA RAS# CAS#
R
C1
C2
C3
C4
t10
t11 t12 t15 t13 t14 t16
MD(Read)
d1
d2
d3
d4
Figure 7-7: EDO-DRAM Read Timing
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 48
Epson Research and Development Vancouver Design Center
Table 7-7: EDO DRAM Read Timing Symbol t1 t2 Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 t10 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address setup time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t12 Access time from RAS# (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) Access time from RAS# (REG[22h] bits [3:2] = 01) t13 t14 t15 t16 Access time from CAS# Access time from CAS# precharge, column address Read Data hold after CAS# low Read Data turn-off delay from RAS# 2 2 Parameter Min 25 5 t1 4 t1 3 t1 2.45 t1 2 t1 1.45 t1 0.45 t1 - 1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 1 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 2 t1 - 2 1 t1 - 2 1.45 t1 - 2 2 t1 1 t1 1.55 t1 3 t1 - 11 2 t1 - 11 2.45 t1 - 12 t1 - 10 1.45 t1 - 6 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 49
7.3.2 EDO-DRAM Write Timing
t1
Memory Clock
t2
t3 R
t4
t5
t6
t8
t9
MA RAS# CAS# WE#
C1
C2
C3 t7
C4
t12 t10 t11 t14 t15
t13
MD(Write)
d1
d2
d3
d4
Figure 7-8: EDO-DRAM Write Timing
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 50
Epson Research and Development Vancouver Design Center
Table 7-8: EDO DRAM Write Timing Symbol t1 Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address setup time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t10 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) t12 t13 t14 t15 Write command setup time Write command hold time Write Data setup time Write Data hold time Parameter Min 25 5 t1 4 t1 3 t1 2.45 t1 2 t1 1.45 t1 0.45 t1 - 1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 1 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 2 t1 - 2 1 t1 - 2 1.45 t1 - 2 0.45 t1 - 1 0.45 t1 0.45 t1 - 3 0.45 t1 - 2 2 t1 1 t1 1.55 t1 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 51
7.3.3 EDO-DRAM Read-Write Timing
t1
Memory Clock
t2
t3
t4 C1
t5 C2
t6 C3
MA RAS# CAS# WE#
R
t7
t8 t9
t10
MD(Read) MD(Write)
d1
d2 d3
Figure 7-9: EDO-DRAM Read-Write Timing
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 52
Epson Research and Development Vancouver Design Center
Table 7-9: EDO DRAM Read-Write Timing Symbol t1 Memory clock period Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address setup time Column address hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t7 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) t8 RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bits [3:2] = 01) t9 t10 Read Data turn-off delay from WE# Write Data delay from WE# (REG[22h] bit 7 = 0) Write Data delay from WE# (REG[22h] bit 7 = 1) Parameter Min 25 5 t1 4 t1 3 t1 2.45 t1 2 t1 1.45 t1 0.45 t1 - 1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 2 t1 - 2 1 t1 - 2 1.45 t1 - 2 0 1.45 t1 0.45 t1 2 t1 1 t1 1.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 53
7.3.4 EDO-DRAM CAS Before RAS Refresh Timing
t1
Memory Clock
t2 t3
RAS# CAS#
t4 t6 t5
Figure 7-10: EDO-DRAM CAS Before RAS Refresh Timing
Table 7-10: EDO-DRAM CAS Before RAS Refresh Timing Symbol t1 t2 Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Random read or write cycle time (REG[22h] bits [6:5] = 00) t3 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) t4 CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (REG[22h] bits [3:2] = 00 or 10) CAS# setup time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 00) t6 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) Parameter Min 25 1.45 t1 0.45 t1 5 t1 4 t1 3 t1 2 t1 1 t1 0.45 t1 - 2 1 t1 - 2 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns
t5
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 54
Epson Research and Development Vancouver Design Center
7.3.5 EDO-DRAM Self-Refresh Timing
Stopped for suspend mode Restarted for active mode
t1
Memory Clock
t2
t5
RAS# CAS#
t3 t4
Figure 7-11: EDO-DRAM Self-Refresh Timing
Table 7-11: EDO-DRAM Self-Refresh Timing Symbol t1 t2 t3 Memory clock period RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (REG[22h] bits [3:2] = 00 or 10) CAS# setup time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 00) t5 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) Parameter Min 25 1.45 t1 0.45 t1 2 t1 1 t1 0.45 t1 - 2 1 t1 - 2 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns ns ns
t4
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 55
7.3.6 FPM-DRAM Read Timing
t1
Memory Clock
t2 t3 R t4 C1 t5 C2 t6 C3 t7 t8 t9 C4
MA RAS# CAS#
t10
t11 t12 t13 t14 t15
MD(Read)
d1
d2
d3
d4
Figure 7-12: FPM-DRAM Read Timing
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 56
Epson Research and Development Vancouver Design Center
Table 7-12: FPM DRAM Read Timing Symbol t1 Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address set-up time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t10 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) Access time from RAS# (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t12 Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) Access time from RAS# (REG[22h] bit 4 = 1 and bits [3:2] = 01) Access time from RAS# (REG[22h] bit 4 = 0 and bits [3:2] = 01) t13 t14 t15 Access time from CAS# Access time from CAS# precharge Read Data hold from CAS# or RAS# 2 Parameter Min 40 5 t1 4 t1 3 t1 2 t1 1.45 t1 1 t1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 0.45 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 1.45 t1 - 2 2.45 t1 - 2 1 t1 - 2 2 t1 - 2 1.55 t1 2.55 t1 1 t1 2 t1 2 t1 - 2 3 t1 - 2 1.45 t1 - 2 2.45 t1 - 2 0.45 t1 - 1 1 t1 - 2 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 57
7.3.7 FPM-DRAM Write Timing
t1
Memory Clock
t2 t3 t4 R C1 t5 C2 t6 C3 t7 t8 C4 t9
MA RAS# CAS# WE#
t12 t10 t11 t14 t15
t13
MD(Write)
d1
d2
d3
d4
Figure 7-13: FPM-DRAM Write Timing
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 58
Epson Research and Development Vancouver Design Center
Table 7-13: FPM-DRAM Write Timing Symbol t1 Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 t7 t8 t9 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address set-up time Column address hold time CAS# pulse width CAS# precharge time RAS# hold time RAS# precharge time (REG[22h] bits [3:2] = 00) t10 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t11 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) t12 t13 t14 t15 Write command setup time Write command hold time Write Data setup time Write Data hold time Parameter Min 40 5 t1 4 t1 3 t1 2 t1 1.45 t1 1 t1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 0.45 t1 - 1 0.45 t1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 1.45 t1 - 2 2.45 t1 - 2 1 t1 - 2 2 t1 - 2 0.45 t1 - 1 0.45 t1 0.45 t1 - 3 0.45 t1 - 2 1.55 t1 2.55 t1 1 t1 2 t1 0.55 t1 + 1 0.55 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 59
7.3.8 FPM-DRAM Read-Write Timing
t1
Memory Clock
t2 t3 t4 R C1 t5 C2 t6 C3
MA RAS# CAS# WE#
t7
t8 t9
t10
MD(Read) MD(Write)
d1
d2 d3
Figure 7-14: FPM-DRAM Read-Write Timing
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 60
Epson Research and Development Vancouver Design Center
Table 7-14: FPM-DRAM Read-Write Timing Symbol t1 Memory clock Random read or write cycle time (REG[22h] bits [6:5] = 00) t2 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) Row address setup time (REG[22h] bits [3:2] = 00) t3 Row address setup time (REG[22h] bits [3:2] = 01) Row address setup time (REG[22h] bits [3:2] = 10) t4 t5 t6 Row address hold time (REG[22h] bits [3:2] = 00 or 10) Row address hold time (REG[22h] bits [3:2] = 01) Column address set-up time Column address hold time RAS# precharge time (REG[22h] bits [3:2] = 0) t7 RAS# precharge time (REG[22h] bits [3:2] = 01) RAS# precharge time (REG[22h] bits [3:2] = 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 00 or 10) t8 RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 00 or 10) RAS# to CAS# delay time (REG[22h] bit 4 = 1 and bits [3:2] = 01) RAS# to CAS# delay time (REG[22h] bit 4 = 0 and bits [3:2] = 01) t9 t10 Read Data turn-off delay from CAS# Write Data enable delay from WE# Parameter Min 40 5 t1 4 t1 3 t1 2 t1 1.45 t1 1 t1 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 0.45 t1 - 1 2 t1 - 1 1.45 t1 - 1 1 t1 - 1 1.45 t1 - 2 2.45 t1 - 2 1 t1 - 2 2 t1 - 2 2 0.45 t1 1.55 t1 2.55 t1 1 t1 2 t1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 61
7.3.9 FPM-DRAM CAS# Before RAS# Refresh Timing
t1
Memory Clock
t2 t3
RAS#
CAS#
t4 t6 t5
Figure 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing
Table 7-15: FPM-DRAM CAS# Before RAS# Refresh Timing Symbol t1 t2 Memory clock RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Random read or write cycle time (REG[22h] bits [6:5] = 00) t3 Random read or write cycle time (REG[22h] bits [6:5] = 01) Random read or write cycle time (REG[22h] bits [6:5] = 10) t4 t5 t6 CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (CAS# before RAS# refresh) RAS# precharge time (REG[22h] bits [3:2] = 00) RAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Parameter Min 40 2 t1 1 t1 5 t1 4 t1 3 t1 2 t1 1 t1 0.45 t1 - 2 2.45 t1 - 1 1.45 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 62
Epson Research and Development Vancouver Design Center
7.3.10 FPM-DRAM Self-Refresh Timing
Stopped for suspend mode Restarted for active mode
t1
Memory Clock
t5 t2
RAS# CAS#
t3 t4
Figure 7-16: FPM-DRAM CBR Self-Refresh Timing
Table 7-16: FPM-DRAM CBR Self-Refresh Timing Symbol t1 t2 t3 t4 t5 Memory clock RAS# to CAS# precharge time (REG[22h] bits [3:2] = 00) RAS# to CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# precharge time (REG[22h] bits [3:2] = 00) CAS# precharge time (REG[22h] bits [3:2] = 01 or 10) CAS# setup time (CAS# before RAS# refresh) RAS# precharge time (REG[22h] bits [3:2] = 00) RAS# precharge time (REG[22h] bits [3:2] = 01 or 10) Parameter Min 40 2 t1 1 t1 2 t1 1 t1 0.45 t1 - 2 2.45 t1 - 1 1.45 t1 - 1 Typ Max Units ns ns ns ns ns ns ns ns
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 63
7.4 Display Interface 7.4.1 Power-On/Reset Timing
TRESET#
RESET#
LCD ENABLE (REG[0Dh] bit 0)
LCDPWR
Inactive
Active
FPFRAME
Active
FPLINE FPSHIFT FPDAT[15:0] DRDY
Active t1 t2
Figure 7-17: LCD Panel Power-On/Reset Timing
Table 7-17: LCD Panel Power-On/Reset Timing Symbol TRESET# t1 t2 RESET# pulse time LCD Enable bit high to FPLINE, FPSHIFT, FPDAT[15:0], DRDY active FPLINE, FPSHIFT, FPDAT[15:0], DRDY active to LCDPWR, on and FPFRAME active 128 Parameter Min 100 Typ Max Units us ns Frames
TFPFRAME + 6TPCLK
Note Where TFPFRAME is the period of FPFRAME and TPCLK is the period of the pixel clock.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 64
Epson Research and Development Vancouver Design Center
7.4.2 Suspend Timing
SUSPEND# Software Suspend Note 1
t1
CLKI t2 LCDPWR FPFRAME Active t4 FPLINE DRDY
Note 2 t3 Inactive t5 Active
Active
Inactive
Active
FPSHIFT FPDAT[15:0]
Active t6
Active t7 Not Allowed Allowed
Memory Access
Allowed
Figure 7-18: LCD Panel Suspend Timing
Table 7-18: LCD Panel Suspend Timing Symbol t1 t2 t3 t4 t5 t6 t7 Parameter LCDPWR inactive to CLKI inactive SUSPEND# active to FPFRAME, LCDPWR inactive First CLKI after SUSPEND# inactive to FPFRAME, LCDPWR active LCDPWR inactive to FPLINE, FPSHIFT, FPDAT[15:0], DRDY active First CLKI after SUSPEND# inactive to FPLINE, FPSHIFT, FPDAT[15:0], DRDY active LCDPWR inactive to Memory Access not allowed First CLKI after SUSPEND# inactive to Memory Access allowed 0 0 8 Min 128 0 Typ Max 1 1 128 Units Frames Frames Frames Frames Frames MCLK MCLK
Note 1. t3, t5, and t7 are measured from the first CLKI after SUSPEND# inactive. 2. CLKI may be active throughout SUSPEND# active. 3. Where MCLK is the period of the memory clock.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 65
7.4.3 Single Monochrome 4-Bit Panel Timing
VDP FPFRAME FPLINE MOD UD[3:0], UD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE239 LINE240
VNDP
LINE1
LINE2
FPLINE MOD HDP FPSHIFT UD3 UD2 UD1 UD0
1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-317 1-318 1-319 1-320
HNDP
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel
Figure 7-19: Single Monochrome 4-Bit Panel Timing VDP = VNDP = HDP = HNDP = Vertical Display Period Vertical Non-Display Period Horizontal Display Period Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 66
Epson Research and Development Vancouver Design Center
Sync Timing
FPFRAME
t1
t2
t3
t4
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t7 t9 t10 t11 t8 t12
FPSHIFT
t13 1 t14 2
UD[3:0]
Figure 7-20: Single Monochrome 4-Bit Panel A.C. Timing
Table 7-19: Single Monochrome 4-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t4min t5min t6min t9min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0] setup to FPSHIFT falling edge UD[3:0] hold to FPSHIFT falling edge Min note 2 9 9 note 3 note 4 note 5 t14 + 2 4 note 6 18 2 2 2 2 Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1) Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0]) + 1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 25] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 67
7.4.4 Single Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-633 1-634 1-635 1-636 1-637 1-638 1-639 1-640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-21: Single Monochrome 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 68
Epson Research and Development Vancouver Design Center
t1
Sync Timing
FPFRAME
t3
t2
t4
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t7 t9 t10 t11 t8 t12
FPSHIFT
t13 t14 1 2
UD[3:0] LD[3:0]
Figure 7-22: Single Monochrome 8-Bit Panel A.C. Timing
Table 7-20: Single Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t4min t5min t6min t9min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge Min note 2 9 9 note 3 note 4 note 5 t14 + 4 8 note 6 18 4 4 4 4 Typ Max Units Ts (note 1) Ts
Ts Ts Ts Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0]) + 1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 23] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 14] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 69
7.4.5 Single Color 4-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP
HNDP
FPSHIFT UD3 UD2 UD1 UD0
1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 1-B3 1-R4 1-G4 1-B4 1-B319 1-R320 1-G320 1-B320
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-23: Single Color 4-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 70
Epson Research and Development Vancouver Design Center
t1
Sync Timing
FPFRAME
t3
t2
t4
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t7 t9 t10 t11 t8 t12
FPSHIFT
t13 1 t14 2
UD[3:0]
Figure 7-24: Single Color 4-Bit Panel A.C. Timing
Table 7-21: Single Color 4-Bit Panel A.C. Timing Symbol Parameter t1 FPFRAME setup to FPLINE falling edge t2 FPFRAME hold from FPLINE falling edge t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t4min t5min t6min t9min FPLINE pulse width FPLINE period MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT pulse width high FPSHIFT pulse width low UD[3:0], setup to FPSHIFT falling edge UD[3:0], hold from FPSHIFT falling edge Min note 2 9 9 note 3 note 4 note 5 t14 + 0.5 1 note 6 19 0.45 0.45 0.45 0.45 Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1) Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 26] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 71
7.4.6 Single Color 8-Bit Panel Timing (Format 1)
VDP
VNDP
FPFRAME FPLINE
UD[3:0], LD[3:0]
LINE1
LINE2
LINE3
LINE4
LINE479 LINE480
LINE1
LINE2
FPLINE
HDP HNDP
FPSHIFT
FPSHIFT2 UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6 1-G6 1-R7 1-B7 1-G8 1-R9 1-B9 1-G10 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-B10 1-B11 1-G12 1-R13 1-B13 1-G14 1-R15 1-B15 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15 1-R16 1-B16 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640
1-G11 1-G16
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-25: Single Color 8-Bit Panel Timing (Format 1) VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 72
Epson Research and Development Vancouver Design Center
t1
Sync Timing
FPFRAME
t3
t2
t4
FPLINE
Data Timing
FPLINE
t5a t5b t8a t9 t6 t10 t7 t11
FPSHIFT
t8b
FPSHIFT2
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-26: Single Color 8-Bit Panel A.C. Timing (Format 1)
Table 7-22: Single Color 8-Bit Panel A.C. Timing (Format 1) Symbol t1 t2 t3 t4 t5a t5b t6 t7 t8a t8b t9 t10 t11 t12 t13 1. 2. 3. 4. 5. 6. 7. Ts t1min t4min t5min t5min t8min t8min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE pulse width FPLINE period FPSHIFT2 falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPLINE falling edge to FPSHIFT2 rising, FPSHIFT falling edge FPSHIFT2, FPSHIFT period FPSHIFT falling edge to FPLINE falling edge FPSHIFT2 falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising edge FPSHIFT2, FPSHIFT pulse width high FPSHIFT2, FPSHIFT pulse width low UD[3:0], LD[3:0] setup to FPSHIFT2 rising, FPSHIFT falling edge UD[3:0], LD[3:0] hold from FPSHIFT2 rising, FPSHIFT falling edge Min note 2 9 9 note 3 note 4 note 5 t14 + 2 4 note 6 note 7 18 2 2 1 1 Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1) Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t4min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 27]+T11 Ts = [((REG[05h] bits [4:0]) + 1)*8 - 27] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18]+T11 Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 73
7.4.7 Single Color 8-Bit Panel Timing (Format 2)
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP
HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3 1-B3 1-R4 1-G4 1-B4 1-R5 1-G 5 1-B5 1-R6 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8 1-G638 1-B638 1-R639 1-G639 1-B639 1-R640 1-G640 1-B640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-27: Single Color 8-Bit Panel Timing (Format 2) VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 74
Epson Research and Development Vancouver Design Center
Sync Timing
FPFRAME
t1
t2
t4
t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-28: Single Color 8-Bit Panel A.C. Timing (Format 2)
Table 7-23: Single Color 8-Bit Panel A.C. Timing (Format 2) Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 note 4 note 5 note 6 t14 + 2 2 1 1 1 1 18 Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 26] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 75
7.4.8 Single Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[7:0], LD[7:0]
LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 LINE1 LINE2
FPLINE MOD
HDP HNDP
FPSHIFT UD7 UD6 UD5 UD4 UD3 UD2 UD1 UD0 LD7 LD6 LD5 LD4 LD3 LD2 LD1 LD0
1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6 1-G6 1-R7 1-B7 1-G8 1-R9 1-B9 1-B11 1-G12 1-R13 1-B13 1-G14 1-R15 1-G635 1-G636 1-R637 1-B637 1-G638 1-R639 1-B639 1-G640 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640
1-G10 1-B15 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-G16 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15
1-B10 1-R16 1-G11 1-B16
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-29: Single Color 16-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 76
Epson Research and Development Vancouver Design Center
Sync Timing
FPFRAME
t1
t2
t4
t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[7:0] LD[7:0]
Figure 7-30: Single Color 16-Bit Panel A.C. Timing
Table 7-24: Single Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[7:0], LD[7:0] setup to FPSHIFT falling edge UD[7:0], LD[7:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 note 4 note 5 note 6 t14 + 3 5 2 2 2 2 18 Ts Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [(REG[05h] bits [4:0]) + 1)*8 - 25] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 16] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 77
7.4.9 Dual Monochrome 8-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242
FPLINE MOD
HDP HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-1 1-2 1-3 1-4 241-1 241-2 241-3 241-4 1-5 1-6 1-7 1-8 241-5 241-6 241-7 241-8 1-637 1-638 1-639 1-640 241-637 241-638 241-639 241-640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-31: Dual Monochrome 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 78
Epson Research and Development Vancouver Design Center
Sync Timing
FPFRAME
t1
t2
t4
t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-32: Dual Monochrome 8-Bit Panel A.C. Timing
Table 7-25: Dual Monochrome 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 note 4 note 5 note 6 t14 + 2 4 2 2 2 2 10 Typ Max Units Ts (note 1) Ts
Ts Ts Ts Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 17] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 8] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 79
7.4.10 Dual Color 8-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[3:0], LD[3:0]
LINE 1/241 LINE 2/242 LINE 239/479 LINE 240/480 LINE 1/241
FPLINE MOD
HDP HNDP
FPSHIFT UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0
1-R 1 1-G1 1-B1 1-R2 1-G 2 1-B2 1-R 3 1-G3 1-B3 1-R4 1-G4 1-B4 1-R 5 1-G5 1-B5 1-R6 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8 1-B639 1-R640 1-G640 1-B640 2 41B639 241R640 241G640 241B640
241-R 1 241-G2 241-B3
241-R5 241-G6 241-B7
241-G1 24 1-B2 241-R 4 241-G 5 241-B6 241-R8 241-B1 241-R3 241-G4 241-B5 241-R7 241-G8 241-R 2 241-G3 241-B4 241-R 6 241-G7 241-B8
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-33: Dual Color 8-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 80
Epson Research and Development Vancouver Design Center
t1
t2
Sync Timing
FPFRAME
t4 t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[3:0] LD[3:0]
Figure 7-34: Dual Color 8-Bit Panel A.C. Timing
Table 7-26: Dual Color 8-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[3:0], LD[3:0] setup to FPSHIFT falling edge UD[3:0], LD[3:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 note 4 note 5 note 6 t14 + 1 1 0.45 0.45 0.45 0.45 11 Ts Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 9] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 81
7.4.11 Dual Color 16-Bit Panel Timing
VDP
VNDP
FPFRAME FPLINE MOD UD[7:0], LD[7:0]
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244 LINE 239/479 LINE 240/480 LINE 1/241 LINE 2/242
FPLINE MOD
HDP HNDP
FPSHIFT UD7, LD7 UD6, LD6 UD5, LD5 UD4, LD4 UD3, LD3 UD2, LD2 UD1, LD1 UD0, LD0
1-R1, 241-R1 1-G1, 241-G 1 1-B1, 241-B1 1-R2, 241-R2 1-G2, 241-G 2 1-B2, 241-B2 1-R3, 241-R3 1-G3, 241-G 3 1-B3, 241-B 3 1-R4, 241-R4 1-G4, 241-G 4 1-B4, 241-B 4 1-R5, 241-R5 1-G5, 241-G 5 1-B5, 241-B 5 1-R6, 241-R6 1-G 638, 241-G638 1-B638, 241-B638 1-R639, 241-R639 1-G 639, 241-G63 9 1-B639, 241-B639 1-R640, 241-R640 1-G640, 241-G640 1-B640, 241-B640
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 7-35: Dual Color 16-Bit Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 82
Epson Research and Development Vancouver Design Center
t1
t2
Sync Timing
FPFRAME
t4 t3
FPLINE
t5
MOD
Data Timing
FPLINE
t6 t8 t7 t14 t11 t9 t10
FPSHIFT
t12 t13 1 2
UD[7:0] LD[7:0]
Figure 7-36: Dual Color 16-Bit Panel A.C. Timing
Table 7-27: Dual Color 16-Bit Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6. Ts t1min t3min t5min t6min t7min Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD delay from FPLINE falling edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high UD[7:0], LD[7:0] setup to FPSHIFT falling edge UD[7:0], LD[7:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 9 note 3 9 note 4 note 5 note 6 t14 + 2 2 1 1 1 1 10 Ts Ts Ts Ts Ts Ts Ts Typ Max Units Ts (note 1)
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = t3min - 9Ts = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0]) + 1)*8] Ts = [((REG[04h] bits [6:0])+1)*8 - 1] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 18] Ts = [((REG[05h] bits [4:0]) + 1)*8 - 9] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 83
7.4.12 16-Bit TFT Panel Timing
VNDP
VDP
FPFRAME FPLINE R[5:1], G[5:0], B[5:1] DRDY
LINE480 LINE1 LINE480
FPLINE
HNDP1 HDP HNDP2
FPSHIFT
DRDY
R[5:1] G[5:0] B[5:1]
1-1 1-1 1-1
1-2 1-2 1-2
1-640 1-640 1-640
Note: DRDY is used to indicate the first pixel Example Timing for 640x480 panel
Figure 7-37: 16-Bit TFT Panel Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = HNDP1 + HNDP2 = ((REG[05h] bits [4:0]) + 1)*8Ts
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 84
Epson Research and Development Vancouver Design Center
t8 t9
FPFRAME
t12
FPLINE
t6
FPLINE
t7 t17 t15
DRDY
t14 t1 t2 t3 t11 t13 t16
FPSHIFT
t4 t5 1 2 t10 639 640
R[5:1] G[5:0] B[5:1]
Note: DRDY is used to indicate the first pixel
Figure 7-38: TFT A.C. Timing
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 85
Table 7-28: TFT A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Ts t6min t7min t8 min t9min t10min t12min t14min t15min t17min FPSHIFT period FPSHIFT pulse width high FPSHIFT pulse width low data setup to FPSHIFT falling edge data hold from FPSHIFT falling edge FPLINE cycle time FPLINE pulse width low FPFRAME cycle time FPFRAME pulse width low horizontal display period FPLINE setup to FPSHIFT falling edge FPFRAME falling edge to FPLINE falling edge phase difference DRDY to FPSHIFT falling edge setup time DRDY pulse width DRDY falling edge to FPLINE falling edge DRDY hold from FPSHIFT falling edge FPLINE Falling edge to DRDY active Parameter Min 1 0.45 0.45 0.45 0.45 note 2 note 3 note 4 note 5 note 6 0.45 note 7 0.45 note 8 note 9 0.45 note 10 250 Ts Ts Ts Ts Typ Max Units Ts (note 1) Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts = [((REG[07h] bits [3:0])+1)*8] Ts = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [5:0])+1)] lines = [((REG[0Ch] bits [2:0])+1)] lines = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8] Ts = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8 - 2] Ts = [((REG[05h] bits [4:0])+1)*8 - ((REG[06h] bits [4:0])+1)*8 + 2]
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 86
Epson Research and Development Vancouver Design Center
7.4.13 CRT Timing
Example Timing for 640x480 CRT
VNDP
VDP
VRTC HRTC DACP[7:0] BLANK#
LINE480 LINE1 LINE480
HRTC
HNDP1 HDP HNDP2
DACCLK
BLANK#
DACD[7:0]
1-1
1-2
1-640
Figure 7-39: CRT Timing VDP VNDP HDP HNDP = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = (REG[09h] bits [1:0], REG[08h] bits [7:0]) + 1 = (REG[0Ah] bits [5:0]) + 1 = ((REG[04h] bits [6:0]) + 1)*8Ts = ((REG[05h] bits [4:0]) + 1)*8Ts = HNDP1 + HNDP2
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 87
t8 t9
VRTC
t12
HRTC
t6
HRTC
t7
t15
BLANK#
t1 t2 t3 t11 t13
t14 t16
DACCLK
t4
t5 1 2 t10 639 640
DACD[7:0]
Figure 7-40: CRT A.C. Timing
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 88
Epson Research and Development Vancouver Design Center
Table 7-29: CRT A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 1. 2. 3. 4. 5. 6. 7. 8. 9. Ts t6min t7min t8 min t9min t10min t12min t14min t15min DACCLK period DACCLK pulse width high DACCLK pulse width low data setup to DACCLK rising edge data hold from DACCLK rising edge HRTC cycle time HRTC pulse width (shown active low) VRTC cycle time VRTC pulse width (shown active low) horizontal display period HRTC setup to DACCLK rising edge VRTC falling edge to FPLINE falling edge phase difference BLANK# to DACCLK rising edge setup time BLANK# pulse width BLANK# falling edge to HRTC falling edge BLANK# hold from DACCLK rising edge Parameter Min 1 0.45 0.45 0.45 0.45 note 2 note 3 note 4 note 5 note 6 0.45 note 7 0.45 note 8 note 9 0.45 Ts Ts Ts Typ Max Units Ts (note 1) Ts Ts Ts Ts
= pixel clock period = memory clock, [memory clock]/2, [memory clock]/3, [memory clock]/4 (see REG[19h] bits [1:0]) = [((REG[04h] bits [6:0])+1)*8 + ((REG[05h] bits [4:0])+1)*8] Ts = [((REG[07h] bits [3:0])+1)*8] Ts = [((REG[09h] bits [1:0], REG[08h] bits [7:0])+1) + ((REG[0Ah] bits [6:0])+1)] lines = [((REG[0Ch] bits [2:0])+1)] lines = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8] Ts = [((REG[04h] bits [6:0])+1)*8] Ts = [((REG[06h] bits [4:0])+1)*8 - 2] Ts
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 89
7.4.14 External RAMDAC Read / Write Timing
Read
AB[20:0] CS# M/R# DACRS[1:0]
t1
t2
Valid RD# Command (depends on CPU bus)
t3 t4
DACRD#
Write
Valid WR# command (depends on CPU bus)
t5
DACWR#
t6
Figure 7-41: Generic Bus RAMDAC Read / Write Timing Table 7-30: Generic Bus RAMDAC Read / Write Timing Symbol TBCLK t1 t2 t3 t4 t5 t6 Bus clock period AB[20:0], CS#, M/R# delay to DACRS[1:0] DACRS[1:0] hold from AB[20:0], CS#, M/R# negated Valid RD# command to DACRS[1:0] delay DACRD# hold from valid RD# command negated Valid WR# command to DACWR# delay DACWR# pulse width low 8 3 2 TBCLK 2.45 TBCLK 2.55 TBCLK Parameter Min 30 10 10 33 14 Typ Max Units ns ns ns ns ns ns ns
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 90
Epson Research and Development Vancouver Design Center
8 Registers
8.1 Register Mapping
The SED1354 registers are all memory mapped. The system must provide the external address decoding through the CS# and M/R# input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001. See the table below:
Table 8-1: SED1354 Addressing CS# M/R# Register access: 0 0 * REG[00h] is addressed when AB[5:0] = 0 * REG[01h] is addressed when AB[5:0] = 1 * REG[n] is addressed when AB[5:0] = n Memory access: the 2M byte display buffer is addressed by AB[20:0] SED1354 not selected Access
0 1
1 X
8.2 Register Descriptions
Note Unless specified otherwise, all register bits are reset to 0 during power up. Reserved bits should be written 0 when programming unless otherwise noted.
8.2.1 Revision Code Register
Revision Code Register
REG[00h] Product Code Product Code Product Code Product Code Product Code Product Code Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code Bit 1 RO Revision Code Bit 0
bits 7-2 bits 1-0
Product Code Bits [5:0] This is a read-only register that indicates the product code of the chip. The product code is 000001. Revision Code Bits [1:0] This is a read-only register that indicates the revision code of the chip. The revision code is 00.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 91
8.2.2 Memory Configuration Registers
Memory Configuration Register
REG[01h] n/a Refresh Rate Bit 2 Refresh Rate Bit 1 Refresh Rate Bit 0 n/a WE# Control n/a RW Memory Type
bits 6-4
DRAM Refresh Rate Select Bits [2:0] These bits specify the amount of divide from the input clock (CLKI) to generate the DRAM refresh clock rate, which is equal to 2(ValueOfTheseBits + 6).
Table 8-2: DRAM Refresh Rate Selection Refresh Rate Bits [2:0] 000 001 010 011 100 101 110 111 CLKI Divide Amount 64 128 256 512 1024 2048 4096 8192 Refresh Rate for 33MHz CLKI 520 kHz 260 kHz 130 kHz 65 kHz 33 kHz 16 kHz 8 kHz 4 kHz DRAM Refresh Time/256 Cycles 0.5 ms 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms
bit 2 bit 0
WE# Control When this bit = 1, 2-WE# DRAM is selected. When this bit = 0 2-CAS# DRAM is selected. Memory Type When this bit = 1, FPM-DRAM is selected. When this bit = 0, EDO-DRAM is selected. This bit should be changed only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see SED1354 Programming Notes and Examples, document number X19A-G-002-xx.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 92
Epson Research and Development Vancouver Design Center
8.2.3 Panel/Monitor Configuration Registers
Panel Type Register
REG[02h] n/a n/a Panel Data Width Bit 1 Panel Data Width Bit 0 Panel Data Color/Mono Format Select Panel Select Dual/Single Panel Select RW TFT/Passive LCD Panel Select
bits 5-4
Panel Data Width Bits [1:0] These bits select passive LCD/TFT panel data width size.
Table 8-3: Panel Data Width Selection Panel Data Width Bits [1:0] 00 01 10 11 Passive LCD Panel Data Width Size 4-bit 8-bit 16-bit Reserved TFT Panel Data Width Size 9-bit 12-bit 16-bit Reserved
bit 3
Panel Data Format Select When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. This bit must be set to 0 for all other LCD panel formats. Color/Mono Panel Select When this bit = 1, color passive LCD panel is selected. When this bit = 0, monochrome passive LCD panel is selected. Dual/Single Panel Select When this bit = 1, dual passive LCD panel is selected. When this bit = 0, single passive LCD panel is selected. Setting this bit for single panel mode should be done only when the Half Frame Buffer is idle. The Half Frame Buffer is idle during vertical non-display periods or while in suspend mode. For programming information, see SED1354 Programming Notes and Examples, document number X19A-G-002-xx. TFT/Passive LCD Panel Select When this bit = 1, TFT panel is selected. When this bit = 0, passive LCD panel is selected.
bit 2
bit 1
bit 0
MOD Rate Register
REG[03h] n/a n/a MOD Rate Bit 5 MOD Rate Bit 4 MOD Rate Bit 3 MOD Rate Bit 2 MOD Rate Bit 1 RW MOD Rate Bit 0
bits 5-0
MOD Rate Bits [5:0] For a non-zero value these bits specify the number of FPLINE between toggles of the MOD output signal. When these bits are all 0's the MOD output signal toggles every FPFRAME. These bits are for passive LCD panels only.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 93
Horizontal Display Width Register
REG[04h] n/a Horizontal Display Width Bit 6 Horizontal Display Width Bit 5 Horizontal Display Width Bit 4 Horizontal Display Width Bit 3 Horizontal Display Width Bit 2 Horizontal Display Width Bit 1 RW Horizontal Display Width Bit 0
bits 6-0
Horizontal Display Width Bits [6:0] These bits specify the LCD panel and/or the CRT horizontal display width as follows. Contents of this Register = (Horizontal Display Width / 8) - 1 For passive LCD panels the Horizontal Display Width must be divisible by 16, and for TFT LCD panels/CRTs the Horizontal Display Width must be divisible by 8. The maximum horizontal display width is 1024 pixels. Note This register must be programmed such that REG[04h] 3 (32 pixels)
Horizontal Non-Display Period Register
REG[05h] n/a n/a n/a Horizontal Non-Display Period Bit 4 Horizontal Non-Display Period Bit 3 Horizontal Non-Display Period Bit 2 Horizontal Non-Display Period Bit 1 RW Horizontal Non-Display Period Bit 0
bits 4-0
Horizontal Non-Display Period Bits [4:0] These bits specify the horizontal non-display period width in 8-pixel resolution as follows. Contents of this Register = (Horizontal Non-Display Period / 8) - 1 The minimum value which should be programmed into this register is 3 (32 pixels). The maximum value which can be programmed into this register is 1F, which gives a horizontal non-display period width of 256 pixels. Note This register must be programmed such that REG[05h] 3 and (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
HRTC/FPLINE Start Position Register
REG[06h] n/a n/a n/a HRTC/ FPLINE Start Position Bit 4 HRTC/ FPLINE Start Position Bit 3 HRTC/ FPLINE Start Position Bit 2 HRTC/ FPLINE Start Position Bit 1 RW HRTC/ FPLINE Start Position Bit 0
bits 4-0
HRTC/FPLINE Start Position Bits [4:0] For CRTs and TFTs, these bits specify the delay from the start of the horizontal non-display period to the leading edge of the HRTC pulse and FPLINE pulse respectively. Contents of this Register = (HRTC/FPLINE Start Position / 8) - 1 The maximum HRTC start delay is 256 pixels. Note This register must be programmed such that (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 94
Epson Research and Development Vancouver Design Center
HRTC/FPLINE Pulse Width Register
REG[07h] HRTC Polarity Select FPLINE Polarity Select HRTC/ FPLINE Pulse Width Bit 3 HRTC/ FPLINE Pulse Width Bit 2 HRTC/ FPLINE Pulse Width Bit 1 RW HRTC/ FPLINE Pulse Width Bit 0
n/a
n/a
bit 7
HRTC Polarity Select For CRTs, this bit selects the polarity of the HRTC. When this bit = 1, the HRTC pulse is active high. When this bit = 0, the HRTC pulse is active low. FPLINE Polarity Select This bit selects the polarity of the FPLINE for TFT and passive LCD. When this bit = 1, the FPLINE pulse is active high for TFT and active low for passive LCD. When this bit = 0, the FPLINE pulse is active low for TFT and active high for passive LCD.
Table 8-4: FPLINE Polarity Selection FPLINE Polarity Select 0 1 Passive LCD FPLINE Polarity active high active low TFT FPLINE Polarity active low active high
bit 6
bits 3-0
HRTC/FPLINE Pulse Width Bits [3:0] For CRTs and TFTs, these bits specify the pulse width of HRTC and FPLINE respectively. For passive LCDs, FPLINE is automatically created and these bits have no effect. HRTC/FPLINE pulse width (pixels) = (HRTC/FPLINE Pulse Width Bits [3:0] + 1) x 8. The maximum HRTC pulse width is 128 pixels. Note This register must be programmed such that (REG[05h] + 1) (REG[06h] + 1) + (REG[07h] bits [3:0] + 1)
Vertical Display Height Register 0
REG[08h] Vertical Display Height Bit 7 Vertical Display Height Bit 6 Vertical Display Height Bit 5 Vertical Display Height Bit 4 Vertical Display Height Bit 3 Vertical Display Height Bit 2 Vertical Display Height Bit 1 RW Vertical Display Height Bit 0
Vertical Display Height Register 1
REG[09h] n/a n/a n/a n/a n/a n/a Vertical Display Height Bit 9 RW Vertical Display Height Bit 8
REG[08h] bits 7-0 REG[09h] bits 1-0
Vertical Display Height Bits [9:0] These bits specify the LCD panel and/or the CRT vertical display height, in 1-line resolution. For a dual LCD panel only configuration, this register should be programmed to half the panel size. Vertical display height in number of lines = (ContentsOfThisRegister) + 1. The maximum vertical display height is 1024 lines.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 95
Vertical Non-Display Period Register
REG[0Ah] Vertical Non-Display Period Status (RO) Vertical Non-Display Period Bit 5 Vertical Non-Display Period Bit 4 Vertical Non-Display Period Bit 3 Vertical Non-Display Period Bit 2 Vertical Non-Display Period Bit 1 RW Vertical Non-Display Period Bit 0
n/a
bit 7
Vertical Non-Display Period Status This is a read-only status bit. A "1" indicates that a vertical non-display period is occurring. A "0" indicates that display output is in a vertical display period. Note When configured for a dual panel, this bit will toggle at twice the frame rate.
bits 5-0
Vertical Non-Display Period Bits [5:0] These bits specify the vertical non-display period height in 1-line resolution. Vertical non-display period height in number of lines = (ContentsOfThisRegister) + 1. The maximum vertical non-display period height is 64 lines. Note This register must be programmed such that REG[0Ah] 1 and (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
VRTC/FPFRAME Start Position Register
REG[0Bh] VRTC/ FPFRAME Start Position Bit 5 VRTC/ FPFRAME Start Position Bit 4 VRTC/ FPFRAME Start Position Bit 3 VRTC/ FPFRAME Start Position Bit 2 VRTC/ FPFRAME Start Position Bit 1 RW VRTC/ FPFRAME Start Position Bit 0
n/a
n/a
bits 5-0
VRTC/FPFRAME Start Position Bits [5:0] For CRTs and TFTs, these bits specify the delay in lines from the start of the vertical non-display period to the leading edge of the VRTC pulse and FPFRAME pulse respectively. For passive LCDs, FPFRAME is automatically created and these bits have no effect. VRTC/FPFRAME start position (lines) = VRTC/FPFRAME Start Position Bits [5:0] + 1. The maximum VRTC start delay is 64 lines. Note This register must be programmed such that (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 96
Epson Research and Development Vancouver Design Center
VRTC/FPFRAME Pulse Width Register
REG[0Ch] FPFRAME VRTC Polarity Polarity Select Select VRTC/ FPFRAME Pulse Width Bit 2 VRTC/ FPFRAME Pulse Width Bit 1 RW VRTC/ FPFRAME Pulse Width Bit 0
n/a
n/a
n/a
bit 7
VRTC Polarity Select For CRTs, this bit selects the polarity of the VRTC. When this bit = 1, the VRTC pulse is active high. When this bit = 0, the VRTC pulse is active low. FPFRAME Polarity Select This bit selects the polarity of the FPFRAME for TFT and passive LCD. When this bit = 1, the FPFRAME pulse is active high for TFT and active low for passive LCD. When this bit = 0, the FRAME pulse is active low for TFT and active high for passive LCD.
Table 8-5: FPFRAME Polarity Selection FPFRAME Polarity Select 0 1 Passive LCD FPFRAME Polarity active high active low TFT FPFRAME Polarity active low active high
bit 6
bits 2-0
VRTC/FPFRAME Pulse Width Bits [2:0] For CRTs and TFTs, these bits specify the pulse width of VRTC and FPFRAME respectively. For passive LCDs, FPFRAME is automatically created and these bits have no effect. VRTC/FPFRAME pulse width (lines) = VRTC/FPFRAME Pulse Width Bits [2:0] + 1. The maximum VRTC pulse width is 8 lines. Note This register must be programmed such that (REG[0Ah] bits [5:0] + 1) (REG[0Bh] + 1) + (REG[0Ch] bits [2:0] + 1)
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 97
8.2.4 Display Configuration Registers
Display Mode Register
REG[0Dh] Simultaneous Display Option Select Bit 1 Simultaneous Number Of Display Bits/Pixel Option Select Select Bit 2 Bit 0 Number Of Bits/Pixel Select Bit 1 Number Of Bits/Pixel Select Bit 0 RW
n/a
CRT Enable
LCD Enable
bits 6-5
Simultaneous Display Option Select Bits [1:0] These bits are used to select one of four different simultaneous display mode options: Normal, Line Doubling, Interlace, or Even Scan Only. The purpose of these modes is to manipulate the vertical resolution of the image so that it fits on both CRT, typically 640 x 480, and LCD. The following gives descriptions of the four modes using a 640x480 CRT as an example:
Table 8-6: Simultaneous Display Option Selection Simultaneous Display Option Select Bits [1:0] 00 01 10 11 Simultaneous Display Option Normal Line Doubling Interlace Even Scan Only
Note 1. Line doubling option is not supported with dual panel. 2. Dual Panel Considerations When configured for a dual panel LCD and using Simultaneous Display, the Half Frame Buffer Disable, REG[1Bh] bit 0, must be set to 1. This will result in a lower contrast on the LCD panel, which then may require adjustment. Normal - the image is the same on both displays, i.e. 640x240. CRT parameters determine the LCD image. The LCD image will appear to be washed out due to the 1/525 duty cycle of the CRT. Line Doubling - each line is sent to the CRT twice, giving a 640x480 image which has a long aspect ratio. The image on the LCD has each line sent twice but only one FPLINE. This gives a duty cycle of 2/525, which is very close to the LCD only mode duty cycle of 1/242, so the image on the LCD will have almost the same contrast as that of a single LCD. Interlace - odd frames receive odd scan lines and even frames receive even scan lines. The 640x480 image on the CRT will be normal while the image on the 640x240 LCD will appear to be squashed, though text will be readable. Even Scan Only - the 640x480 image on the CRT is normal. The LCD (640x240) only receives the even scan lines. The image on the LCD does not flicker, but it may be hard to read text.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 98
Epson Research and Development Vancouver Design Center
bits 4-2
Number of Bits-Per-Pixel Select Bits [2:0] These bits select the number of bits-per-pixel (bpp) for the displayed data. Note 15 and 16-bpp modes bypass the LUT and are supported as 12-bpp on passive panels and 15/16bpp on TFT panels. These modes are not supported on CRT. See Figure 10-2: "15/16 Bit-PerPixel Format Memory Organization," on page 117 for a description of passive panel support.
Table 8-7: Number of Bits-Per-Pixel Selection Number Of Bits-Per-Pixel Select Bits [2:0] 000 001 010 011 100 101 110-111 Number of Bits-Per-Pixel 1 2 4 8 15 16 Reserved
bit 1
CRT Enable This bit enables the CRT control signals. Note REG[02h] bit 1 must = 0 when in CRT only mode.
bit 0
LCD Enable This bit enables the LCD control signals. Programming this bit from a 0 to a 1 starts the LCD power-on sequence. Programming this bit from a 1 to a 0 starts the LCD power-off sequence.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 99
Screen 1 Line Compare Register 0
REG[0Eh] RW Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Line Line Line Line Line Line Line Line Compare Bit 7 Compare Bit 6 Compare Bit 5 Compare Bit 4 Compare Bit 3 Compare Bit 2 Compare Bit 1 Compare Bit 0
Screen 1 Line Compare Register 1
REG[0Fh] n/a n/a n/a n/a n/a n/a RW Screen 1 Screen 1 Line Line Compare Bit 9 Compare Bit 8
REG[0Eh] bits 7-0 REG[0Fh] bits 1-0
Screen 1 Line Compare Bits [9:0] In split screen mode, the panel is divided into screen 1 and screen 2, with screen 1 above screen 2. This is the 10-bit value that specifies the screen 1 size in 1-line resolution for split screen mode. Split screen 1 vertical size in number of lines = (ContentsOfThisRegister) + 1. Where ContentsOfThisRegister is a 10-bit value comprising of these registers. The maximum screen 1 vertical size is 1024 lines. Screen 2 is visible only if the screen 1 line compare is less than the vertical panel size. The starting address for screen 1 is given by the Screen 1 Display Start Address registers. The starting address for screen 2 is given by the Screen 2 Display Start Address registers. See Section 10.2, "Image Manipulation" on page 118 and SED1354 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for more details. Note For normal operation (no split screen) this register must be set greater than the vertical display height REG[08h] and REG[09h] (e.g. set to 3FFh).
Screen 1 Display Start Address Register 0
REG[10h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Screen 1 Display Start Address Register 1
REG[11h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Screen 1 Display Start Address Register 2
REG[12h] n/a n/a n/a n/a RW Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16
REG[10h] bits 7-0 REG[11h] bits 7-0 REG[12h] bits 3-0
Screen 1 Start Address Bits [19:0] This register forms the 20-bit address for the starting word of the screen 1 image in the display buffer. Note that this is a word address. An entry of 0000h into these registers represents the first word of display memory, an entry of 0001h represents the second word of display memory, and so on. See Section 10, "Display Configuration" on page 116 for details.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 100
Epson Research and Development Vancouver Design Center
Screen 2 Display Start Address Register 0 RW
REG[13h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Screen 2 Display Start Address Register 1
REG[14h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Screen 2 Display Start Address Register 2
REG[15h] n/a n/a n/a n/a RW Start Address Start Address Start Address Start Address Bit 19 Bit 18 Bit 17 Bit 16
REG[13h] bits 7-0 REG[14h] bits 7-0 REG[15h] bits 3-0
Screen 2 Start Address Bits [19:0] This register forms the 20-bit address for the starting word of the screen 2 image in the display buffer. Note that this is a word address. An entry of 0000h into these registers represents the first word of display memory, an entry of 0001h represents the second word of display memory, and so on. See Section 10, "Display Configuration" on page 116 for details.
Memory Address Offset Register 0
REG[16h] Memory Address Offset Bit 7 Memory Address Offset Bit 6 Memory Address Offset Bit 5 Memory Address Offset Bit 4 Memory Address Offset Bit 3 Memory Address Offset Bit 2 Memory Address Offset Bit 1 RW Memory Address Offset Bit 0
Memory Address Offset Register 1
REG[17h] n/a n/a n/a n/a n/a n/a Memory Address Offset Bit 9 RW Memory Address Offset Bit 8
REG[16] bits 7-0 REG[17] bits 1-0
Memory Address Offset Bits [9:0] These bits are the 10-bit address offset from the starting word of line "n" to the starting word of line "n + 1". This value is applied to both screen 1 and screen 2. Note This value is in words and must be programmed REG[04h]. A virtual image can be formed by setting this register to a value greater than the width of the display. The displayed image is a window into the larger virtual image. See Section 10, "Display Configuration" on page 116 for details.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 101
b
Pixel Panning Register
REG[18h] RW Screen 2 Screen 2 Screen 2 Screen 2 Screen 1 Screen 1 Screen 1 Screen 1 Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Pixel Panning Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0
This register is used to control the horizontal pixel panning of screen 1 and screen 2. Each screen can be independently panned to the left by programming its respective Pixel Panning Bits to a nonzero value. This value represents the number of pixels panned. The maximum pan value is dependent on the display mode as shown in the table below.
Table 8-8: Pixel Panning Selection Number of Bits-Per-Pixel 1 2 4 8 15/16 Screen 2 Pixel Panning Bits Used Bits [3:0] Bits [2:0] Bits [1:0] Bit 0 ---
Smooth horizontal panning can be achieved by a combination of this register and the Display Start Address register. See Section 10, "Display Configuration" on page 116 and SED1354 Programming Notes and Examples, document number X19A-G-002-xx, Section 4 for details. bits 7-4 bits 3-0 Screen 2 Pixel Panning Bits [3:0] Pixel panning bits for screen 2. Screen 1 Pixel Panning Bits [3:0] Pixel panning bits for screen 1.
8.2.5 Clock Configuration Register
Clock Configuration Register
REG[19h] n/a n/a n/a n/a n/a MCLK Divide Select PCLK Divide Select Bit 1 RW PCLK Divide Select Bit 0
bit 2
MCLK Divide Select When this bit = 1 the memory clock (MCLK) frequency is half of the input clock frequency. When this bit = 0 the memory clock frequency is equal to the input clock frequency. PCLK Divide Select Bits [1:0] These bits determine the amount of divide from the memory clock to generate the pixel clock (PCLK):
Table 8-9: PCLK Divide Selection PCLK Divide Select Bits [1:0] 00 01 10 11 MCLK/PCLK Frequency Ratio 1 2 3 4
bits 1-0
See Section 11.2, "Frame Rate Calculation" on page 120 for selection of PCLK frequency.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 102
Epson Research and Development Vancouver Design Center
8.2.6 Power Save Configuration Registers
Power Save Configuration Register
REG[1Ah] n/a n/a n/a n/a LCD Power Disable Suspend Refresh Select Bit 1 Suspend Refresh Select Bit 0 RW Software Suspend Mode Enable
bit 3
LCD Power Disable When this bit = 1 the LCDPWR output is directly forced to the Off state. The LCDPWR "On/Off" state is configured by MD10 at the rising edge of RESET#. When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic. See Table 5-8: "Summary of Power On / Reset Options," on page 31. Suspend Refresh Select Bits [1:0] These bits specify the type of DRAM refresh to use in Suspend mode.
Table 8-10: Suspend Refresh Selection Suspend Refresh Select Bits [1:0] 00 01 1x DRAM Refresh Type CBR Refresh Self-Refresh No Refresh
bits 2-1
Note These bits should not be changed when suspend mode is enabled. bit 0 Software Suspend Mode Enable When this bit = 1 software suspend mode is enabled. When this bit = 0 software suspend mode is disabled.
8.2.7 Miscellaneous Registers
Miscellaneous Disable Register
REG[1Bh] Host Interface Disable n/a n/a n/a n/a n/a n/a RW Half Frame Buffer Disable
bit 7
Host Interface Disable This bit must be programmed to 0 to enable the Host Interface. This bit goes high on reset. When this bit is high, all memory and all registers except REG[1Ah] (read-only), REG[28h] through REG[2Fh], and REG[1Bh] are inaccessible.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 103
bit 0
Half Frame Buffer Disable This bit is used to disable the Half Frame Buffer. When this bit = 1, the Half Frame Buffer is disabled. When this bit = 0, the Half Frame Buffer is enabled. When a single panel is selected, the Half Frame Buffer is automatically disabled and this bit has no hardware effect. The Half Frame Buffer is needed to fully support dual panels. Disabling the Half Frame Buffer reduces memory bandwidth requirements and increases the supportable pixel clock frequency, but results in reduced contrast on the LCD panel. This mode is not normally used except in special circumstances such as simultaneous display on a CRT and dual panel LCD. See Section 11.2 on page 120 for details. Note The Half Frame Buffer should be disabled only when idle. The Half Frame Buffer is idle during vertical non-display periods (i.e. when REG[0Ah] bit 7 = 1), or while in suspend mode. For programming information, see SED1354 Programming Notes and Examples, document number X19A-G-002-xx.
MD Configuration Readback Register 0
REG[1Ch] MD7 Status MD6 Status MD5 Status MD4 Status MD3 Status MD2 Status MD1 Status RO MD0 Status
MD Configuration Readback Register 1
REG[1Dh] MD15 Status MD14 Status MD13 Status MD12 Status MD11 Status MD10 Status MD9 Status MD8 Status RO
REG[1Ch] bits 7-0 REG[1Dh] bits 7-0
MD[15:0] Configuration Status These are read-only status bits for the MD[15:0] pins configuration status at the rising edge of RESET#. See Table 5-8: "Summary of Power On / Reset Options," on page 31.
GPIO Configuration Register 0
REG[1Eh] GPIO7 Pin IO Config. GPIO6 Pin IO Config. GPIO5 Pin IO Config. GPIO4 Pin IO Config. GPIO3 Pin IO Config. GPIO2 Pin IO Config. GPIO1 Pin IO Config. RW GPIO0 Pin IO Config.
bit 7
GPIO7 Pin IO Configuration When this bit = 1, GPIO7 is configured as an output. When this bit = 0 (default), GPIO7 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO7, otherwise the DACWR# pin is controlled automatically and this bit will have no effect on hardware. GPIO6 Pin IO Configuration When this bit = 1, GPIO6 is configured as an output. When this bit = 0 (default), GPIO6 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO6, otherwise the DACP0 pin is controlled automatically and this bit will have no effect on hardware.
bit 6
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 104
Epson Research and Development Vancouver Design Center
bit 5
GPIO5 Pin IO Configuration When this bit = 1, GPIO5 is configured as an output. When this bit = 0 (default), GPIO5 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO5, otherwise the BLANK# pin is controlled automatically and this bit will have no effect on hardware. GPIO4 Pin IO Configuration When this bit = 1, GPIO4 is configured as an output. When this bit = 0 (default), GPIO4 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO4, otherwise the DACRD# pin is controlled automatically and this bit will have no effect on hardware. GPIO3 Pin IO Configuration When this bit = 1, GPIO3 is configured as an output. When this bit = 0 (default), GPIO3 is configured as an input. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO3, otherwise the MA9 pin is controlled automatically and this bit will have no effect on hardware. GPIO2 Pin IO Configuration When this bit = 1, GPIO2 is configured as an output. When this bit = 0 (default), GPIO2 is configured as an input. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO2, otherwise the MA10 pin is controlled automatically and this bit will have no effect on hardware. GPIO1 Pin IO Configuration When this bit = 1, GPIO1 is configured as an output. When this bit = 0 (default), GPIO1 is configured as an input. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO1, otherwise the MA11 pin is controlled automatically and this bit will have no effect on hardware. GPIO0 Pin IO Configuration When this bit = 1, GPIO0 is configured as an output. When this bit = 0 (default), GPIO0 is configured as an input.
bit 4
bit 3
bit 2
bit 1
bit 0
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 105
GPIO Configuration Register 1
REG[1Fh] n/a n/a n/a n/a GPIO11 Pin IO Config. GPIO10 Pin IO Config. GPIO9 Pin IO Config. RW GPIO8 Pin IO Config.
bit 3
GPIO11 Pin IO Configuration When this bit = 1, GPIO11 is configured as an output. When this bit = 0 (default), GPIO11 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO11, otherwise the VRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO10 Pin IO Configuration When this bit = 1, GPIO10 is configured as an output. When this bit = 0 (default), GPIO10 is configured as an input. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO10, otherwise the HRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO9 Pin IO Configuration When this bit = 1, GPIO9 is configured as an output. When this bit = 0 (default), GPIO9 is configured as an input. Note GPIO9 and GPIO8 must always be set to the same function (both to input or both to output). The MD8 pin must be high at the rising edge of RESET# to enable GPIO9, otherwise the DACRS1 pin is controlled automatically and this bit will have no effect on hardware.
bit 2
bit 1
bit 0
GPIO8 Pin IO Configuration When this bit = 1, GPIO8 is configured as an output. When this bit = 0 (default), GPIO8 is configured as an input. Note GPIO8 and GPIO9 must always be set to the same function (both to input or both to output). The MD8 pin must be high at the rising edge of RESET# to enable GPIO8, otherwise the DACRS0 pin is controlled automatically and this bit will have no effect on hardware.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 106
Epson Research and Development Vancouver Design Center
GPIO Status / Control Register 0
REG[20h] GPIO7 Pin IO Status GPIO6 Pin IO Status GPIO5 Pin IO Status GPIO4 Pin IO Status GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status RW GPIO0 Pin IO Status
bit 7
GPIO7 Pin IO Status When GPIO7 is configured as an output, a "1" in this bit drives GPIO7 to high and a "0" in this bit drives GPIO7 to low. When GPIO7 is configured as an input, a read from this bit returns the status of GPIO7. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO7, otherwise the DACWR# pin is controlled automatically and this bit will have no effect on hardware. GPIO6 Pin IO Status When GPIO6 is configured as an output, a "1" in this bit drives GPIO6 to high and a "0" in this bit drives GPIO6 to low. When GPIO6 is configured as an input, a read from this bit returns the status of GPIO6. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO6, otherwise the DACP0 pin is controlled automatically and this bit will have no effect on hardware. GPIO5 Pin IO Status When GPIO5 is configured as an output, a "1" in this bit drives GPIO5 to high and a "0" in this bit drives GPIO5 to low. When GPIO5 is configured as an input, a read from this bit returns the status of GPIO5. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO5, otherwise the BLANK# pin is controlled automatically and this bit will have no effect on hardware. GPIO4 Pin IO Status When GPIO4 is configured as an output, a "1" in this bit drives GPIO4 to high and a "0" in this bit drives GPIO4 to low. When GPIO4 is configured as an input, a read from this bit returns the status of GPIO4. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO4, otherwise the DACRD# pin is controlled automatically and this bit will have no effect on hardware. GPIO3 Pin IO Status When GPIO3 is configured as an output, a "1" in this bit drives GPIO3 to high and a "0" in this bit drives GPIO3 to low. When GPIO3 is configured as an input, a read from this bit returns the status of GPIO3. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO3, otherwise the MA9 pin is controlled automatically and this bit will have no effect on hardware. GPIO2 Pin IO Status When GPIO2 is configured as an output, a "1" in this bit drives GPIO2 to high and a "0" in this bit drives GPIO2 to low. When GPIO2 is configured as an input, a read from this bit returns the status of GPIO2. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO2, otherwise the MA11 pin is controlled automatically and this bit will have no effect on hardware. GPIO1 Pin IO Status When GPIO1 is configured as an output, a "1" in this bit drives GPIO1 to high and a "0" in this bit drives GPIO1 to low. When GPIO1 is configured as an input, a read from this bit returns the status of GPIO1. Note the MD[7:6] pins must be properly configured at the rising edge of RESET# to enable GPIO1, otherwise the MA10 pin is controlled automatically and this bit will have no effect on hardware. GPIO0 Pin IO Status When GPIO0 is configured as an output, a "1" in this bit drives GPIO0 to high and a "0" in this bit drives GPIO0 to low. When GPIO0 is configured as an input, a read from this bit returns the status of GPIO0.
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 107
GPIO Status / Control Register 1 REG[21h] GPO Control n/a n/a n/a GPIO11 Pin IO Status GPIO10 Pin IO Status GPIO9 Pin IO Status
RW GPIO8 Pin IO Status
bit 7
GPO Control This bit is used to control the state of the SUSPEND# pin when it is configured as GPO. The SUSPEND# pin can be used as a power-down input (SUSPEND#) or as an output (GPO) possibly used for controlling the LCD backlight power: * When MD9 = 0 at rising edge of RESET#, SUSPEND# is an active-low Schmitt input used to put the SED1354 into suspend mode - see Section 13, "Power Save Modes" on page 128 for details. * When MD[10:9] = 01 at rising edge of RESET#, SUSPEND# is an output with a reset state of 1. * When MD[10:9] = 11 at rising edge of RESET#, SUSPEND# is an output with a reset state of 0. When this bit = 0 the GPO output is set to the reset state. When this bit = 1 the GPO output pin is set to the inverse of the reset state.
bit 3
GPIO11 Pin IO Status When GPIO11 is configured as an output, a "1" in this bit drives GPIO11 to high and a "0" in this bit drives GPIO11 to low. When GPIO11 is configured as an input, a read from this bit returns the status of GPIO11. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO11, otherwise the VRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO10 Pin IO Status When GPIO10 is configured as an output, a "1" in this bit drives GPIO10 to high and a "0" in this bit drives GPIO10 to low. When GPIO10 is configured as an input, a read from this bit returns the status of GPIO10. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO10, otherwise the HRTC pin is controlled automatically and this bit will have no effect on hardware. GPIO9 Pin IO Status When GPIO9 is configured as an output, a "1" in this bit drives GPIO9 to high and a "0" in this bit drives GPIO9 to low. When GPIO9 is configured as an input, a read from this bit returns the status of GPIO9. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO9, otherwise the DACRS1 pin is controlled automatically and this bit will have no effect on hardware. GPIO8 Pin IO Status When GPIO8 is configured as an output, a "1" in this bit drives GPIO8 to high and a "0" in this bit drives GPIO8 to low. When GPIO8 is configured as an input, a read from this bit returns the status of GPIO8. Note the MD8 pin must be high at the rising edge of RESET# to enable GPIO8, otherwise the DACRS0 pin is controlled automatically and this bit will have no effect on hardware.
bit 2
bit 1
bit 0
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 108
Epson Research and Development Vancouver Design Center
Performance Enhancement Register 0
REG[22h] EDO ReadWrite Delay RC Timing Value Bit 1 RC Timing Value Bit 0 RAS# to CAS# Delay RAS# Precharge Timing Bit 1 RAS# Precharge Timing Bit 0 n/a RW Reserved
Note Changing this register to non-zero value, or to a different non-zero value, should be done only when there are no read/write DRAM cycles. This condition occurs when both the Display FIFO is disabled (REG[23h] bit 7 = 1) and the Half Frame Buffer is disabled (REG[1Bh] bit 0 = 1). For programming information, see SED1354 Programming Notes and Examples, document number X19A-G-002-xx. bit 7 EDO Read-Write Delay This bit is used for EDO-DRAM to select the delay during the read-write transition. A "0" selects 2 MCLK delay for the read-write transition. A "1" selects 1 MCLK delay for the read-write DRAM. This bit has no effect for FPM-DRAM which always uses 1 MCLK delay for the read-write transition. This bit may be programmed to 1 when the MCLK frequency is less than 30MHz. RC Timing Value (NRC) Bits [1:0] These bits select the DRAM random-cycle timing parameter, tRC. These bits specify the number (NRC) of MCLK periods (TM) used to create tRC. NRC should be chosen to meet tRC as well as tRAS, the RAS pulse width. Use the following two formulae to calculate NRC then choose the larger value. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRC NRC = Round-Up (tRC/TM) = Round-Up (tRAS/TM + NRP) = Round-Up (tRAS/TM + 1.55) = (NRC) TM
Table 8-11: Minimum Memory Timing Selection REG[22h] Bits [6:5] 00 01 10 11 NRC 5 4 3 Reserved Minimum Random Cycle Width (tRC) 5 TM 4 TM 3 TM Reserved
bits 6-5
if NRP = 1 or 2 if NRP = 1.5
The resulting tRC is related to NRC as follows: tRC
bit 4
RAS# to CAS# Delay (NRCD) This bit selects the DRAM RAS# to CAS# delay parameter, tRCD. This bit specifies the number (NRCD) of MCLK periods (TM) used to create tRCD. NRCD must be chosen to satisfy the RAS# access time, tRAC. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRCD = Round-Up((tRAC + 5)/TM - 1) =2 = Round-Up(tRAC/TM - 1) = Round-Up(tRAC/TM - 0.45) if EDO and NRP = 1 or 2 if EDO and NRP = 1.5 if FPM and NRP = 1 or 2 if FPM and NRP = 1.5
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 109
Note that for EDO-DRAM and NRP = 1.5, this bit is automatically forced to 0 to select 2 MCLK for NRCD. This is done to satisfy the CAS# address setup time, tASC. The resulting tRC is related to NRCD as follows: tRC tRC tRC tRC = (NRCD) TM = (1.5) TM = (NRCD + 0.5) TM = (NRCD) TM if EDO and NRP = 1 or 2 if EDO and NRP = 1.5 if FPM and NRP = 1 or 2 if FPM and NRP = 1.5
Table 8-12: RAS-to-CAS Delay Timing Select REG[22h] Bit 4 0 1 NRCD 2 1 RAS# to CAS# Delay (tRCD) 2 TM 1 TM
bits 3-2
RAS# Precharge Timing (NRP) Bits [1:0] Minimum Memory Timing for RAS precharge These bits select the DRAM RAS# Precharge timing parameter, tRP. These bits specify the number (NRP) of MCLK periods (TM) used to create tRP - see the following formulae. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRP =1 = 1.5 =2 if (tRP/TM) < 1 if 1 (tRP/TM) < 1.45 if (tRP/TM) 1.45 if FPM refresh cycle and NRP = 1 or 2 for all other
The resulting tRC is related to NRP as follows: tRC tRC = (NRP + 0.5) TM = (NRP) TM
Table 8-13: RAS Precharge Timing Select REG[22h] Bits [3:2] 00 01 10 11 NRP 2 1.5 1 Reserved RAS# Precharge Width (tRP) 2 TM 1.5 TM 1 TM Reserved
Optimal DRAM Timing The following table contains the optimally programmed values of NRC, NRP, and NRCD for different DRAM types, at maximum MCLK frequencies.
Table 8-14: Optimal NRC, NRP, and NRCD Values at Maximum MCLK Frequency DRAM Type EDO FPM DRAM Speed
(ns)
TM (ns) 25 30 33 40 50
NRC (#MCLK) 4 4 5 4 3
NRP (#MCLK) 1.5 1.5 2 1.5 1.5
NRCD (#MCLK) 2 2 2 2 1
50 60 70 60 70
bit 0
Reserved Must be set to 0.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 110
Epson Research and Development Vancouver Design Center
Performance Enhancement Register 1
REG[23h] Display FIFO Disable n/a n/a Display FIFO Threshold Bit 4 Display FIFO Threshold Bit 3 Display FIFO Threshold Bit 2 Display FIFO Threshold Bit 1 Display FIFO Threshold Bit 0
bit 7
Display FIFO Disable When this bit = 1 the display FIFO is disabled and all data outputs are forced to zero (i.e. the screen is blanked). This allows the SED1354 to be dedicated to service CPU to memory accesses. When this bit = 0 the display FIFO is enabled. Display FIFO Threshold Bits [4:0] These bits should be set to a value of 10h upon initialization as this provides the best overall performance for all display modes.
bits 4-0
8.2.8 Look-Up Table Registers
The SED1354 has three internal 16 position, 4-bit wide Look-Up Tables. The 4-bit value programmed into each table position determines the color weighting of display data; the output gray shade is derived from the Green Look-Up Table. These tables are bypassed in 15/16-bpp mode. These three 16 position Look-Up Tables can be arranged in many different configurations to accommodate all the gray shade / color display modes. Look-Up Table Address Register
REG[24h] n/a n/a RGB Index Bit 1 RGB Index Bit 0 LUT Address Bit 3 LUT Address Bit 2 LUT Address Bit 1 RW LUT Address Bit 0
bits 5-4
RGB Index Bits [1:0] These bits are also used to provide access to the three internal Look-Up Tables (RGB).
Table 8-15: RGB Index Selection RGB Index Bits [1:0] 00 01 10 11 Look-Up Table Access Auto-Increment R, G, B LUT Auto-Increment Red LUT only Auto-Increment Green LUT only Auto-Increment Blue LUT only Pointer Sequence R[n], G[n], B[n], R[n+1], G[n+1] . . . R[n], R[n+1], R[n+2] . . . G[n], G[n+1], G[n+2] . . . B[n], B[n+1], B[n+2] . . .
A write to this register with RGB Index bits = 00 selected will position the internal pointer to the Red LUT. Each read/write access to the LUT data will increment the counter to point to the next LUT in order (R to G to B to R...). A read/write access to the Blue LUT will also automatically increment the LUT address by 1. This provides an efficient method for sequential writing of RGB data. When the RGB Index bits = 01, 10, or 11, the internal pointer always points to the respective R, G, or B LUT. A read/write access to the LUT data will increment the LUT address by 1.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 111
bits 3-0
LUT Address Bits [3:0] These 4 bits provide a pointer into the 16 position Look-Up Table currently selected for CPU read/write access. The Look-Up Table configuration (e.g. 1/2/4 banks) does not affect the read/write access from the CPU as all 16 positions can be accessed sequentially.
Look-Up Table Data Register
REG[26h] n/a n/a n/a n/a LUT Data Bit 3 LUT Data Bit 2 LUT Data Bit 1 RW LUT Data Bit 0
bits 3-0
LUT Data Bits [3:0] These 4 bits are the gray shade/color values used for display data output. They are programmed into the 4-bit Look-Up Table positions pointed to by LUT Address bits [3:0] and RGB Index bits [1:0] (if in color display modes). For example: in a 16-level gray shade display mode, a data value of 0001b (4 bits-per-pixel) will point to Look-Up Table position one and display the 4-bit gray shade corresponding to the value programmed into that location.
Look-Up Table Bank Select Register
REG[27h] n/a n/a Red Bank Select Bit 1 Red Bank Select Bit 0 Blue Bank Select Bit 1 Blue Bank Select Bit 0 Green Bank Select Bit 1 RW Green Bank Select Bit 0
bit 5-4
Red Bank Select Bits [1:0] In 2-bpp mode, the 16 position Red LUT is arranged into four, 4 position "banks." These two bits control which bank is currently selected. In 8-bpp mode, the 16 position Red LUT is arranged into two, 8 position "banks." Only bit 0 of these two bits controls which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, 15/16-bpp mode, or all monochrome modes.
bit 3-2
Blue Bank Select Bits [1:0] In both 2-bpp and 8-bpp modes, the 16 position Blue LUT is arranged into four 4 position "banks." These two bits control which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, 15/16-bpp mode, or all monochrome modes.
bits 1-0
Green Bank Select Bits [1:0] In 2-bpp mode, the 16 position Green LUT is arranged into four, 4 position "banks." These two bits control which bank is currently selected. In 8-bpp mode, the 16 position Green LUT is arranged into two, 8 position "banks." Only bit 0 of these two bits controls which bank is currently selected. These bits have no effect in 1-bpp, 4-bpp, and 15/16-bpp modes.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 112
Epson Research and Development Vancouver Design Center
8.2.9 External RAMDAC Control Registers
Note 1. In a Little-Endian architecture, the RAMDAC should be connected to the low byte of the CPU data bus and the following registers are accessed at the lower address given for each register (28h, 2Ah, 2Ch, and 2Eh). In a Big-Endian architecture, the RAMDAC should be connected to the high byte of the CPU data bus and the following registers are accessed at the higher address given for each register (29h, 2Bh, 2Dh, and 2Fh). 2. When accessing the External RAMDAC Control registers with either of the architectures described in note 1, accessing the adjacent unused registers is prohibited. 3. To access the RAMDAC registers the CRT enable bit, REG[0Dh] bit 1, must be set to 1.
RAMDAC Pixel Read Mask Register
REG[28h] or REG[29h] RAMDAC Data Bit 7 RAMDAC Data Bit 6 RAMDAC Data Bit 5 RAMDAC Data Bit 4 RAMDAC Data Bit 3 RAMDAC Data Bit 2 RAMDAC Data Bit 1 RW RAMDAC Data Bit 0
bits 7-0
RAMDAC Pixel Read Mask Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 1 and DACRS0 = 0 to the external RAMDAC for a pixel read mask register access. The RAMDAC data must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
RAMDAC Read Mode Address Register
REG[2Ah] or REG[2Bh] RAMDAC Address Bit 7 RAMDAC Address Bit 6 RAMDAC Address Bit 5 RAMDAC Address Bit 4 RAMDAC Address Bit 3 RAMDAC Address Bit 2 RAMDAC Address Bit 1 RW RAMDAC Address Bit 0
bits 7-0
RAMDAC Read Mode Address Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 1 and DACRS0 = 1 to the external RAMDAC for a read-mode address register access. The RAMDAC address must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
RAMDAC Write Mode Address Register
REG[2Ch] or REG[2Dh] RAMDAC Address Bit 7 RAMDAC Address Bit 6 RAMDAC Address Bit 5 RAMDAC Address Bit 4 RAMDAC Address Bit 3 RAMDAC Address Bit 2 RAMDAC Address Bit 1 RW RAMDAC Address Bit 0
bits 7-0
RAMDAC Write Mode Address Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 0 and DACRS0 = 0 to the external RAMDAC for a write-mode address register access. The RAMDAC address must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 113
RAMDAC Palette Data Register
REG[2Eh] or REG[2Fh] RAMDAC Data Bit 7 RAMDAC Data Bit 6 RAMDAC Data Bit 5 RAMDAC Data Bit 4 RAMDAC Data Bit 3 RAMDAC Data Bit 2 RAMDAC Data Bit 1 RW RAMDAC Data Bit 0
bits 7-0
RAMDAC Palette Data Bits [7:0] A CPU read or write to this register will generate a DACRD# or DACWR# pulse and DACRS1 = 0 and DACRS0 = 1 to the external RAMDAC for a palette data register access. The RAMDAC data must be transferred directly between the system data bus and the external RAMDAC through either data bus bits [7:0] in a Little-Endian system or data bus bits [15:8] in a Big-Endian system.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 114
Epson Research and Development Vancouver Design Center
9 Display Buffer
The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0] as shown in the following table.
Table 9-1: SED1354 Addressing CS# M/R# Register access: 0 0 * REG[00h] is addressed when AB[5:0] = 0 * REG[01h] is addressed when AB[5:0] = 1 * REG[n] is addressed when AB[5:0] = n Memory access: the 2M byte display buffer is addressed by AB[20:0] SED1354 not selected Access
0 1
1 X
The display buffer address space is always 2M bytes. However, the physical display buffer may be either 512K bytes or 2M bytes. See Section 5.5, "Summary of Configuration Options" on page 31. The 512K byte display buffer is replicated in the 2M byte address space as shown below.
512K byte Memory
AB[20:0] 000000h
2M byte Memory
Image Buffer Half-Frame Buffer Image Buffer Half-Frame Buffer Image Buffer Half-Frame Buffer Image Buffer Half-Frame Buffer Half-Frame Buffer 17FFFFh 180000h 0FFFFFh 100000h Image Buffer 07FFFFh 080000h
1FFFFFh
Figure 9-1: Display Buffer Addressing
The display buffer will contain an image buffer and may also contain a half-frame buffer.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 115
9.1 Image Buffer
The image buffer contains the formatted display data - see Section 10.1, "Display Mode Data Format" on page 116. The displayed image(s) may take up only a portion of the image buffer; the remaining area can be used for multiple images - possibly for animation or general storage. See Section 10, "Display Configuration" on page 116 for details on the relationship between the image buffer and the display.
9.2 Half Frame Buffer
In dual panel mode, with the half frame buffer enabled, the top of the display buffer is allocated to the half-frame buffer. The size of the half frame buffer is a function of the panel resolution and whether the panel is color or monochrome: Half Frame Buffer Size (in bytes) = (panel width x panel length) * factor / 16 where factor = 4 for color panel = 1 for monochrome panel For example, for a 640x480 8 bpp color panel the half frame buffer size is 75K bytes. In a 512K byte display buffer, the half-frame buffer resides from 6D400h to 7FFFFh. In a 2M byte display buffer, the half-frame buffer resides from 1ED400h to 1FFFFFh.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 116
Epson Research and Development Vancouver Design Center
10 Display Configuration
10.1 Display Mode Data Format
1-bpp: Byte 0
bit 7 A0 A1 A2 A3 A4 A5 A6
bit 0 A7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An)
Panel Display Host Address Display Buffer
2-bpp: Byte 0 Byte 1
bit 7 A0 A4 B0 B4 A1 A5 B1 B5 A2 A6 B2 B6 A3 A7
bit 0 B3 B7
P0 P1 P2 P3 P4 P5 P6 P7
Pn = (An, Bn) Panel Display
Host Address
Display Buffer
4-bpp: bit 7 Byte 0 Byte 1 Byte 2 A0 A2 A4 B0 B2 B4 C0 C2 C4 D0 D2 D4 A1 A3 A5 B1 B3 B5 C1 C3 C5 bit 0 D1 D3 D5 Pn = (An, Bn, Cn, Dn) P0 P1 P2 P3 P4 P5 P6 P7
Panel Display Host Address Display Buffer
8-bpp: bit 7 Byte 0 Byte 1 Byte 2 R0
2
3-3-2 RGB bit 0
1 R01 R00 G02 G01 G00 B0 B00
P0 P1 P2 P3 P4 P5 P6 P7
1 R12 R11 R10 G12 G11 G10 B1 B10 1 R22 R21 R20 G22 G21 G20 B2 B20
Pn = (Rn2-0, Gn 2-0, Bn1-0)
Panel Display Host Address Display Buffer
Figure 10-1: 1/2/4/8 Bit-Per-Pixel Format Memory Organization
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 117
15-bpp: 5-5-5 RGB bit 7 Byte 0 Byte 1 Byte 2 Byte 3 bit 0 G02 G01 G00 B04 B03 B02 B01 B00 R0
4
P0 P1 P2 P3 P4 P5 P6 P7
R03
R0
2
R01
R0
0
G0
4
G03
TFT Pn = (Rn4-0, Gn 4-0, Bn4-0) Passive Pn = (Rn4-1, Gn 4-1, Bn4-1) Panel Display
G12 G11 G10 B14 B13 B12 B11 B10 R14 R13 R12 R11 R10 G14 G13
Host Address
Display Buffer
16-bpp: 5-6-5 RGB bit 7 Byte 0 Byte 1 Byte 2 Byte 3 bit 0 TFT Pn = (Rn4-0, Gn 5-0, Bn4-0) Passive Pn = (Rn4-1, Gn 5-2, Bn4-1) Panel Display G02 G01 G00 B04 B03 B02 B01 B00 R04 R03 R02 R01 R00 G05 G04 G03 G12 G11 G10 B14 B13 B12 B11 B10 R14 R13 R12 R11 R10 G15 G14 G13 P0 P1 P2 P3 P4 P5 P6 P7
Host Address
Display Buffer
Figure 10-2: 15/16 Bit-Per-Pixel Format Memory Organization
Note 1. The Host-to-Display mapping described here assumes that a Little-Endian interface is being used. 2. For 8/15/16 bit-per-pixel formats, Rn, Gn, Bn represent the red, green, and blue color components.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 118
Epson Research and Development Vancouver Design Center
10.2 Image Manipulation
The figure below shows how screen 1 and screen 2 images stored in the image buffer are positioned on the display. The screen 1 and screen 2 images can be parts of a larger virtual image or images. * (REG[17h], REG[16h]) defines the width of the virtual image(s). * (REG[12h], REG[11h], REG[10h]) defines the starting word of the screen 1, (REG[15h], REG[14h], REG[13h]) defines the starting word of the screen 2. * REG[18h] bits [3:0] define the starting pixel within the starting word for screen 1, REG[18h] bits[7:4] define the starting pixel within the starting word for screen 2. * (REG[0Fh],REG[0Eh]) define the last line of screen 1, the remainder of the display is taken up by screen 2. Image Buffer
(REG[12h], REG[11h], REG[10h]) REG[18h] bits [3:0]
Display
((REG[09h], REG[08h])+1) lines
Screen 1
Line 0 Line 1
Screen 1
(REG[15h], REG[14h], REG[13h]) REG[18h] bits [7:4] Line (REG[0Fh], REG[0Eh])
Screen 2 Screen 2
((REG[04h]+1)*8) pixels
(REG[17h], REG[16h])
Figure 10-3: Image Manipulation
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 119
11 Clocking
11.1 Maximum MCLK: PCLK Ratios
Table 11-1: Maximum PCLK Frequency with EDO-DRAM Display type * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Dual Monochrome Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable.
NRC
Maximum PCLK Allowed 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp
5, 4, 3
MCLK
5 4 3 5 4 3
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/3 MCLK/2 MCLK/2
MCLK/3 MCLK/3 MCLK/2 MCLK/3 MCLK/3 MCLK/3
Table 11-2: Maximum PCLK Frequency with FPM-DRAM Display type * Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. * Dual Monochrome Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Monochrome Panel with Half Frame Buffer Enable. * Dual Color Panel with Half Frame Buffer Enabled. * Simultaneous CRT + Dual Color Panel with Half Frame Buffer Enable.
NRC
Maximum PCLK allowed 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp
5, 4, 3
MCLK
5 4 3 5 4 3
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK MCLK/2 MCLK/2 MCLK/2
MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK/2
MCLK/3 MCLK/2 MCLK/2 MCLK/3 MCLK/3 MCLK/2
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 120
Epson Research and Development Vancouver Design Center
11.2 Frame Rate Calculation
The frame rate is calculated using the following formula:
PCLK max FrameRate = ---------------------------------------------------------------------------------------( HDP + HNDP ) x ( VDP + VNDP )
Where:
VDP VNDP HDP HNDP Ts = Vertical Display Period = Vertical Non-Display Period = Horizontal Display Period = Horizontal Non-Display Period = Pixel Clock = REG[09h] bits [1:0], REG[08h] bits [7:0] + 1 = REG[0Ah] bits [5:0] + 1 = in table below = ((REG[04h] bits [6:0]) + 1) * 8Ts = ((REG[05h] bits [4:0]) + 1) * 8Ts = given in table below = PCLK
Table 11-3: Example Frame Rates DRAM Type1 (Speed Grade) Color Depth (bpp) 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 20 13.3 20 13.3 40 Maximum Minimum Pixel Panel Clock HNDP(Ts) (MHz) 32 56 32 56 32 56 32 56 32 56 32 32 32 32 Maximum Frame Rate (Hz) Panel4 80 78 123 119 247 242 243 232 471 441 80 53 123 82 CRT 60 60 85 85 -
Display
Resolution
50ns
EDO-DRAM MClk = 40MHz NRC = 4 NRP = 1.5 NRCD = 2
* Single Panel. * CRT. * Dual Monochrome/Color Panel with Half Frame Buffer Disabled.5 * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled.5
800x6002 640x480 640x240 480x320 320x240
* Dual Color with Half Frame Buffer Enabled. * Dual Mono with Half Frame Buffer Enabled.
800x6002,3 640x480
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 121
Table 11-3: Example Frame Rates DRAM Type1 (Speed Grade) Color Depth (bpp) 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8 16 1/2/4/8/16 1/2/4/8/16 1/2/4/8/16 1/2/4/8 16 1/2/4/8 16 12.5 12.5 12.5 12.5 8.33 12.5 8.33 25 16.5 11 16.5 11 33 Maximum Minimum Pixel Panel Clock HNDP(Ts) (MHz) 32 56 32 56 32 56 32 56 32 56 32 32 32 32 32 56 32 56 32 56 32 56 32 56 32 32 32 32 32 32 32 Maximum Frame Rate (Hz) Panel4 66 65 101 98 203 200 200 196 388 380 66 43 103 68 50 48 77 75 142 136 152 145 294 280 50 77 92 50 33 77 51 CRT 55 55 78 78 60 60 -
Display
Resolution
60ns
EDO-DRAM MClk = 33MHz NRC = 4 NRP = 1.5 NRCD = 2
* Single Panel. * CRT. * Dual Mono/Color Panel with Half Frame Buffer Disabled.5 * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Mono/Color Panel with Half Frame Buffer Disabled.5
800x6002 640x480 640x240 480x320 320x240
* Dual Color with Half Frame Buffer Enabled. * Dual Mono with Half Frame Buffer Enabled. * Single Panel. * CRT. * Dual Mono/Color Panel with Half Frame Buffer Disabled.5 * Simultaneous CRT + Single Panel. * Simultaneous CRT + Dual Mono/Color Panel with Half Frame Buffer Disabled.5
800x6002,3 640x480 800x6002 640x480 640x240 480x320 320x240 800x600
2
60ns
FPM-DRAM
MClk = 25MHz NRC = 4 NRP = 1.5 * Dual Mono with Half Frame Buffer NRCD = 2 Enabled.
640x480 640x400
* Dual Color with Half Frame Buffer Enabled.
800x6002,3 640x480
1. 2. 3. 4. 5.
Must set NRC = 4MCLK. See REG[22h], "Performance Enhancement Register 0". 800x600 @ 16 bpp requires 2M bytes of display buffer for all display types. 800x600 @ 8 bpp on a dual color panel requires 2M bytes of display buffer if the half frame buffer is enabled. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too high for a panel, MCLK should be reduced or PCLK should be divided down. Half Frame Buffer disabled by REG[1Bh] bit 0.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 122
Epson Research and Development Vancouver Design Center
12 Look-Up Table Architecture
Table 12-1: Look-Up Table Configurations Display Mode RED Black & White 4-level gray 16-level gray 2 color 4 color 16 color 256 color 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 2 banks of 8 entries 4-Bit Wide Look-Up Table GREEN 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 2 banks of 8 entries 1 bank of 2 entries 4 banks of 4 entries 1 bank of 16 entries 4 banks of 4 entries BLUE
Indicates the look-up table is not used for that display mode
The following depictions are intended to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the various "banking" configurations.
12.1 Gray Shade Display Modes
1 Bit-Per-Pixel Mode
Green Look-Up Table
0 1 1-bit pixel data 0 Entry 4-bit display data output 1 Select Logic
Figure 12-1: 1 Bit-Per-Pixel - 2-Level Gray-Shade Mode Look-Up Table Architecture
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 123
2 Bit-Per-Pixel Mode
Green Look-Up Table Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [1:0] 2-bit pixel data
00
01 Bank Select Logic 10
Selected Bank 00 Entry 01 Select 4-bit display data output 10 11 Logic
11
Note: the above depiction is intended to show the display data output path only. The CPU R/W access to the individual Look-Up Tables is not affected by the various "banking" configurations.
Figure 12-2: 2 Bit-Per-Pixel - 4-Level Gray-Shade Mode Look-Up Table Architecture
4 Bit-Per-Pixel Mode
Green Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit display data output
4-bit pixel data
Figure 12-3: 4 Bit-Per-Pixel - 16-Level Gray-Shade Mode Look-Up Table Architecture
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 124
Epson Research and Development Vancouver Design Center
12.2 Color Display Modes
1 Bit-Per-Pixel Color Mode
Red Look-Up Table
0 1 1-bit pixel data 0 Entry 4-bit Red data output 1 Select Logic
Green Look-Up Table
0 1 0 Entry 4-bit Green data output 1 Select Logic
Blue Look-Up Table
0 1 0 Entry 4-bit Blue data output 1 Select Logic
Figure 12-4: 1 Bit-Per-Pixel - 2-Level Color Look-Up Table Architecture
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 125
2 Bit-Per-Pixel Color Mode
Red Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [5:4] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Red data output 00
2-bit pixel data
Green Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [1:0] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Green data output 00
Blue Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [3:2] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Blue data output 00
Figure 12-5: 2 Bit-Per-Pixel - 4-Level Color Mode Look-Up Table Architecture
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 126
Epson Research and Development Vancouver Design Center
4 Bit-Per-Pixel Color Mode
Red Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 4-bit pixel data 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit Red data output
Green Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit Green data output
Blue Look-Up Table 0 1 2 3 4 5 6 7 8 9 A B C D E F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Entry Select Logic
4-bit Blue data output
Figure 12-6: 4 Bit-Per-Pixel - 16-Level Color Mode Look-Up Table Architecture
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 127
8 Bit-Per-Pixel Color Mode
256 Color Data Format: 7 6 5 4 3 2 1 0
Bank 0 0 1 2 3 4 5 6 7 Bank 1 8 9 A B C D E F Bank Select bit REG[27h] bit 4 3-bit pixel data
Red Look-Up Table
R2 R1 R0 G2 G1 G0 B1 B0
0
Selected Bank 000 001 010 Entry 4-bit Red data output 011 100 Select Logic 101 110 111
Bank Select Logic 1
Green Look-Up Table
Bank 0 0 1 2 3 4 5 6 7 Bank 1 8 9 A B C D E F Bank Select bit REG[27h] bit 0 3-bit pixel data
0
Selected Bank 000 001 010 Entry 4-bit Green data output 011 100 Select Logic 101 110 111
Bank Select Logic 1
Blue Look-Up Table
Bank 0 0 1 2 3 Bank 1 4 5 6 7 Bank 2 8 9 A B Bank 3 C D E F Bank Select bits [1:0] REG[27h] bits [3:2] 11 01 Bank Select Logic 10 Selected Bank 00 Entry 01 Select 10 11 Logic 4-bit Blue data output 00
2-bit pixel data
Figure 12-7: 8 Bit-Per-Pixel - 256-Level Color Mode Look-Up Table Architecture
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 128
Epson Research and Development Vancouver Design Center
13 Power Save Modes
Two Power Save Modes have been incorporated into the SED1354 to accommodate the important need for power reduction in the hand-held devices market. These modes are hardware suspend and software suspend.
13.1 Hardware Suspend
* Register read/write disallowed. * Memory read/write disallowed. * LCD outputs are forced low (see Note 1 of Section 13.4, "Pin States in Power Save Modes" on page 129). * LCDPWR forced to Off state. * CRT outputs are disabled. * If suspend mode CBR refresh is selected, all internal modules and clocks except the Memory I/F are shut down. * If suspend mode self-refresh or no-refresh is selected, all internal modules and clocks are shut down.
13.2 Software Suspend
* Register read/write allowed except for RAMDAC registers. * Memory read/write disallowed. * LCD outputs are forced low (see Note 1 of Section 13.4, "Pin States in Power Save Modes" on page 129). * LCDPWR forced to Off state. * CRT outputs are disabled. * If suspend mode CBR refresh is selected, all internal modules and clocks except the Host Bus I/F and the Memory I/F are shut down. * If suspend mode self-refresh or no-refresh is selected, all internal modules and clocks except the Host Bus I/F are shut down.
SED1354 X19A-A-002-16
Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 129
13.3 Power Save Mode Function Summary
Table 13-1: Power Save Mode Function Summary Power Save Mode (PSM) Function Display Active? Register Access Possible? Memory Access Possible? Host Bus Interface Running? Memory Interface Running? Yes Yes Yes Yes Yes Normal (Active) No Yes (1) No Yes No (2) Software Suspend No No No No No (2) Hardware Suspend
Note (1) except for RAMDAC registers. (2) Yes if CBR suspend mode refresh is selected.
13.4 Pin States in Power Save Modes
Table 13-2: Pin States in Power Save Modes Pin State Pins LCD outputs LCDPWR DRAM outputs CRT / DAC outputs Host Interface outputs Normal (Active) Active On Active Active Active Software Suspend Forced Low (1) Off Refresh Only (2) Disabled (3) Active (4) Hardware Suspend Forced Low (1) Off Refresh Only (2) Disabled (3) Disabled
Note 1. FPFRAME and FPLINE are forced to their inactive states as defined by REG[0Ch] bit 6 and REG[07h] bit 6 respectively. 2. Selectable: may be CBR refresh, self-refresh or no refresh at all. 3. DACWR#, DACRD#, DACRS0, DACRS1 are active but DACCLK is disabled. 4. Active for non-DAC register access only.
Hardware Functional Specification Issue Date: 99/05/18
SED1354 X19A-A-002-16
Page 130
Epson Research and Development Vancouver Design Center
14 Mechanical Data
14.1 QFP15-128 (SED1354F0A)
QFP15 - 128 pin Unit: mm
16.0 0.4 14.0 0.1 96 65
97
64
Index
128
33
1 0.125 0.1 0.4 1.4 0.1 0.16 0.1
32
14.0 0.1 0.1 0.5 0.2 1.0
Figure 14-1: Mechanical Drawing QFP15-128
SED1354 X19A-A-002-16
16.0 0.4 0~10 Hardware Functional Specification Issue Date: 99/05/18
Epson Research and Development Vancouver Design Center
Page 131
14.2 TQFP15-128 (SED1354F1A)
TQFP15 - 128 pin Unit: mm
16 14
96
0.4 0.1
65
97
64
0.1
14
INDEX 128 33 1 32
0.4
0.1
0.16
+0.05 - 0.03
1.2 max
0.125
+0.05 - 0.025
1
0.1
0 10 0.5 1
0.2
Figure 14-2: Mechanical Drawing TQFP15-128
Hardware Functional Specification Issue Date: 99/05/18
16
0.4
SED1354 X19A-A-002-16
Page 132
Epson Research and Development Vancouver Design Center
14.3 QFP20-144 (SED1354F2A)
QFP20 - 144 pin Unit: mm
22 20
108 109
0.4 0.1
73 72
0.1
20
INDEX 144 1 36 37
0.5
0.2
+0.1 - 0.05
1.4
0.1
1.7 max
0.125
+0.05 - 0.025
0.1
0 10 0.5 1
0.2
Figure 14-3: Mechanical Drawing QFP20-144
SED1354 X19A-A-002-16
22
Hardware Functional Specification Issue Date: 99/05/18
0.4
SED1354 Color Graphics LCD/CRT Controller
Programming Notes and Examples
Document Number: X19A-G-002-06
Copyright (c) 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 3
Table Of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Programming the SED1354 Registers 2.1 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.2 2.2.1 2.2.2 2.2.3 2.3 3 3.1 3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Registers Requiring Special Consideration . . . . . . . . . . . . . . . . . . . . . . . .8 REG[01] bit 0 - Memory Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 REG[22] bits 7-2 - Performance Enhancement Register 0 . . . . . . . . . . . . . . . . . . . .8 REG[02] bit 1 - Dual/Single Panel Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 REG[1B] bit 0 - Half Frame Buffer Disable . . . . . . . . . . . . . . . . . . . . . . . . . . .9 REG[23] Display FIFO: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Initialization Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Re-Programming Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 . . . . . . . . . . . . . . . . . . . . . . 11
Disabling the Half Frame Buffer Sequence:
Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Display Buffer Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Display Buffer Organization 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.3 3.3.1 3.3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades) . . . . . . . . . . . . . 12 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades) . . . . . . . . . . . . . 12 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades) . . . . . . . . . . . . 13 Memory Organization for Eight Bit-per-pixel (256 Colors) . . . . . . . . . . . . . . . . . . 13 Memory Organization for 15 Bit-per-pixel (32768 Colors) . . . . . . . . . . . . . . . . . . . 14 Memory Organization for 16 Bit-per-pixel (65536 Colors) . . . . . . . . . . . . . . . . . . . 14 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Look-Up Table Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Look-Up Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
Advanced Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1.1 4.1.2 4.2 4.2.1 4.2.2 4.3 4.3.1 4.3.2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 . . . . . . . . . . . . . . . . . . . . . . . 30
Panning and Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5
LCD Power Sequencing and Power Save Modes 5.1 5.2 5.3 5.4
Introduction to LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . 30 Introduction to Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Suspend Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 4
Epson Research and Development Vancouver Design Center
5.4.1 5.4.2 5.5 6 6.1
Suspend Enable Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Suspend Disable Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
LCD Enable/Disable Sequencing (Reg[0D] bit 0) . . . . . . . . . . . . . . . . . . . . 32 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.1.1 6.1.2 CRT Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Simultaneous Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
CRT Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7 8
Identifying the SED1354 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Hardware Abstraction Layer (HAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 API for 1354HAL 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Screen Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Color Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Register Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
9
Sample Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.1 9.1.2 Sample code using 1354HAL API . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Sample code without using 1354HAL API . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Supported Panel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Appendix A A.1
Supported Panel Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 5
List Of Tables
Table 2-1: Table 3-1: Table 3-2: Table 3-3: Table 3-4: Table 3-5: Table 3-6: Table 3-7: Table 3-8: Table 3-9: Initializing the SED1354 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Pixel Storage for 1 bpp (2 Colors/Gray Shades) in One Byte of Display Buffer . . . . . . . . . . . 12 Pixel Storage for 2 bpp (4 Colors/Gray Shades) in One Byte of Display Buffer . . . . . . . . . . . 12 Pixel Storage for 4 bpp (16 Colors/Gray Shades) in One Byte of Display Buffer . . . . . . . . . . 13 Pixel Storage for 8 bpp (256 Colors) in One Byte of Display Buffer . . . . . . . . . . . . . . . . 13 Pixel Storage for 15 bpp (32768 Colors) in Two Bytes of Display Buffer . . . . . . . . . . . . . . 14 Pixel Storage for 16 bpp (65536 Colors) in Two Bytes of Display Buffer . . . . . . . . . . . . . . 14 Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Recommended LUT Values for 1 bpp Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18 Recommended LUT Values for 2 bpp Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 3-10: Recommended LUT Values to Simulate VGA Default 16 Color Palette. . . . . . . . . . . . . . . 19 Table 3-11: Recommended LUT Values For 8 bpp Color Mode . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 3-12: Examples of 256 Pixel Colors Using Linear LUT . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3-13: Recommended LUT Values for 1 bpp Gray Shades . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3-14: Recommended LUT Values for 2 bpp Gray Shades . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 3-15: Recommended LUT Values for 8 bpp Gray Shade . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4-1: Table 4-2: Table 6-1: Table 6-2: Table 6-3: Table 6-4: Table 9-1: Table 9-2: Table 9-3: Number of Pixels Panned Using Start Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Active Pixel Pan Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RAMDAC Register Mapping for Little/Big-Endian . . . . . . . . . . . . . . . . . . . . . . . . . 33 Related Register Data for CRT Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 bpp Recommended RAMDAC palette data for Simultaneous Display. . . . . . . . . . . . . . . 35 Related register data for Simultaneous Display. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Passive Single Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Passive Dual Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 TFT Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
List of Figures
Figure 4-1: Figure 4-2: Viewport Inside a Virtual Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 320x240 Single Panel For Split Screen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This guide describes how to program the SED1354 Color Graphics LCD/CRT Controller. The guide presents the basic concepts of the LCD/CRT controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the SED1354. The guide also introduces the hardware Abstraction Layer (HAL), which is designed to simplify the programming of the SED1354. Most SED135x, SED137x and SED138x products support the HAL allowing OEMs to switch chips with relative ease.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 8
Epson Research and Development Vancouver Design Center
2 Programming the SED1354 Registers
This section describes how to program the SED1354 registers that require special consideration. It also provides the correct sequence for initializing the SED1354 and disabling the half frame buffer. For further information on the any of the registers described below, refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx.
2.1 Registers Requiring Special Consideration 2.1.1 REG[01] bit 0 - Memory Type
This bit must not be changed during a DRAM R/W access. Configuring this bit during a DRAM Refresh will not cause any problems. Note This register should be programmed only during initialization and never changed after that. However, it still must be programmed BEFORE the internal blocks start to R/W the memory (see Register Initialization in Section 2.1.5).
2.1.2 REG[22] bits 7-2 - Performance Enhancement Register 0
This bit must not be changed during a DRAM R/W access. Configuring this bit during a DRAM Refresh will not cause any problems. Note This register should be programmed only during initialization and never changed after that. However, it still must be programmed BEFORE the internal blocks start to R/W the memory (see Register Initialization in Section 2.1.5).
2.1.3 REG[02] bit 1 - Dual/Single Panel Type
This bit must not be changed while the Half Frame Buffer (HFB) is active. Note This register should be programmed only during initialization and never changed after that. However, it still must be programmed BEFORE the HFB starts to R/W the memory (see Register Initialization in Section 2.1.5).
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 9
2.1.4 REG[1B] bit 0 - Half Frame Buffer Disable
This bit must not be changed while the HFB is active. This register 'might' be disabled during normal operation for two reasons: 1. 2. to increase bandwidth for simultaneous display. to test 'all' available memory.
To disable the HFB see Section 2.3, "Disabling the Half Frame Buffer Sequence:" on page 11. Note The HFB is enabled after RESET (default condition). It will start to Read and Write the DRAM if the DUAL bit set + (Horizontal resolution > 0) + HFB enabled (default power-on state).
2.1.5 REG[23] Display FIFO:
This register can be asynchronously enabled/disabled. Note The Display FIFO starts to access DRAM after RESET.
2.2 Register Initialization 2.2.1 Initialization Sequence
To initialize the SED1354 after POWER-ON or a HARDWARE RESET, do the following: 1. 2. 3. 4. 5. 6. 7. 8. Enable the host interface (REG[1Bh] bit 7=0). Disable the display FIFO (REG[23h] bit 7=1) after stopping FIFO accesses to the DRAM. Set memory type (REG[01h] bit 0). Set performance register (REG[22h]). Set dual/single panel (REG[02h] bit 1). Program all other registers as required. Enable the display FIFO (REG[23h] bit 7=0). Enable display.
Note The Half Frame Buffer does not actually start to access DRAM until step 5, therefore, this initialization sequence will not cause any problems.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 10
Epson Research and Development Vancouver Design Center
2.2.2 Initialization Example
This section presents an example of how to initialize the SED1354 registers.
Example 1: Initialize the registers for a 16 color 640x480 dual passive LCD using a 16 bit data interface; assume 2M byte of display buffer.
Program the SED1354 registers in the following order with the data supplied. Note that for this example, it is assumed that the arrays "unsigned char RED[16], GREEN[16], BLUE[16]" are defined and initialized for the required colors. For example, RED[2], GREEN[2], and BLUE[2] refer to the color components of pixel value 2. In addition, it is assumed that there is no external RAMDAC since only the LCD is being programmed. Consequently, the RAMDAC registers are not programmed. For code examples, see Section 9, "Sample Code" on page 54. Table 2-1: Initializing the SED1354 Registers
Operation REG[1Bh] = 0x00 REG[23h] = 0x80 REG[01h] = 0x30 REG[22h] = 0x24 REG[02h] = 0x26 REG[03h] = 0x00 REG[04h] = 0x4F REG[05h] = 0x1F REG[06h] = 0x00 REG[07h] = 0x00 REG[08h] = 0xEF REG[09h] = 0x00 REG[0Ah] = 0x01 REG[0Bh] = 0x00 REG[0Ch] = 0x00 REG[0Eh] = 0xFF REG[0Fh] = 0x03 REG[10h] = 0x00 REG[11h] = 0x00 REG[12h] = 0x00 REG[13h] = 0x00 REG[14h] = 0x00 REG[15h] = 0x00 REG[16h] = 0xA0 REG[17h] = 0x00 REG[18h] = 0x00 REG[19h] = 0x01 REG[1Ah] = 0x00 REG[1Eh] = 0x00 REG[1Fh] = 0x00 Description Enable Host Interface Disable the Display FIFO Set Memory Type Set Performance Register Set Dual/Single Panel MOD Rate Horizontal Display Width Horizontal Non-Display Period HSYNC Start Position HSYNC Pulse Width Vertical Display Height Vertical Non-Display Period VSYNC Start Position VSYNC Pulse Width Screen 1 Line Compare Screen 1 Display Start Address
Screen 2 Display Start Address Memory Address Offset Pixel Panning Clock Configuration Power Save Configuration General I/O Configuration
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 11
Table 2-1: Initializing the SED1354 Registers (Continued)
REG[20h] = 0x00 REG[21h] = 0x00 REG[24h] = 0x00 for (index = 0; index < 16; ++index) { REG[26h] = RED[index]; REG[26h] = GREEN[index]; REG[26h] = BLUE[index]; } REG[27h] = 0x00 REG[23h] = 0x10 REG[0Dh] = 0x09 General I/O Control Look-Up Table Address Update Look-Up Table based on the RED[16], GREEN[16], and BLUE[16] tables defined earlier in your program. Look-Up Table Bank Select Enable the Display FIFO Enable Display
2.2.3 Re-Programming Registers
The only register which may require modification after the initialization sequence is the Half Frame Buffer. The Memory Type, DUAL/SINGLE, and the Performance Register bits should never be modified after initialization.
2.3 Disabling the Half Frame Buffer Sequence:
The Half Frame Buffer can be ENABLED asynchronously. To DISABLE the Half Frame Buffer, do the following: 1. 2. Disable the display FIFO REG[23] bit 7=1. Set the horizontal resolution to 0 (REG[04]=0). Setting the horizontal resolution = 0 will shut-off any Half Frame Buffer DRAM accesses within 1024 PCLK's or less (1024 PCLK's is the worst case) Wait for VNDP 1->0->1 transitions (REG[0A] bit 7). Waiting for 1 FRAME delay will guarantee that the Half Frame Buffer is idle. Disable the Half Frame Buffer (REG[1B] bit 0=1). Re-program the horizontal resolution to your original value.
3. 4. 5.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 12
Epson Research and Development Vancouver Design Center
3 Display Buffer
This section discusses how the SED1354 stores pixels in the display buffer and where the display buffer is located.
3.1 Display Buffer Location
The SED1354 requires either a 512K byte or a 2M byte block of memory to be decoded by the system. System logic will determine the location of this memory block; the SDU1354B0C evaluation board decodes the display buffer at the 12M byte location of system memory.
3.2 Display Buffer Organization 3.2.1 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)
Eight pixels are grouped into one byte of display buffer as shown below: Table 3-1: Pixel Storage for 1 bpp (2 Colors/Gray Shades) in One Byte of Display Buffer
Bit 7 Pixel 0 Bit 0 Bit 6 Pixel 1 Bit 0 Bit 5 Pixel 2 Bit 0 Bit 4 Pixel 3 Bit 0 Bit 3 Pixel 4 Bit 0 Bit 2 Pixel 5 Bit 0 Bit 1 Pixel 6 Bit 0 Bit 0 Pixel 7 Bit 0
One bit-per-pixel provides two shades of gray by indexing into positions 0 and 1 of the Green LookUp Table (LUT) and two levels of color by indexing into positions 0 and 1 of the Red/Green/Blue LUTs.
3.2.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)
Four pixels are grouped into one byte of display buffer as shown below: Table 3-2: Pixel Storage for 2 bpp (4 Colors/Gray Shades) in One Byte of Display Buffer
Bit 7 Pixel 0 Bit 1 Bit 6 Pixel 0 Bit 0 Bit 5 Pixel 1 Bit 1 Bit 4 Pixel 1 Bit 0 Bit 3 Pixel 2 Bit 1 Bit 2 Pixel 2 Bit 0 Bit 1 Pixel 3 Bit 1 Bit 0 Pixel 3 Bit 0
Two bit-per-pixel provides four shades of gray by indexing into positions 0 through 3 of the Green LUT and four levels of color by indexing into positions 0 through 3 of the Red/Green/Blue LUTs.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 13
3.2.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)
Two pixels are grouped into one byte of display buffer as shown below: Table 3-3: Pixel Storage for 4 bpp (16 Colors/Gray Shades) in One Byte of Display Buffer
Bit 7 Pixel 0 Bit 3 Bit 6 Pixel 0 Bit 2 Bit 5 Pixel 0 Bit 1 Bit 4 Pixel 0 Bit 0 Bit 3 Pixel 1 Bit 3 Bit 2 Pixel 1 Bit 2 Bit 1 Pixel 1 Bit 1 Bit 0 Pixel 1 Bit 0
Four bit-per-pixel provides sixteen shades of gray by indexing into positions 0 through F of the Green LUT and 16 levels of color by indexing into positions 0 through F of the Red/Green/Blue LUTs.
3.2.4 Memory Organization for Eight Bit-per-pixel (256 Colors)
One pixel is stored in one byte of display buffer as shown below: Table 3-4: Pixel Storage for 8 bpp (256 Colors) in One Byte of Display Buffer
Bit 7 Red Bit 2 Bit 6 Red Bit 1 Bit 5 Red Bit 0 Bit 4 Green Bit 2 Bit 3 Green Bit 1 Bit 2 Green Bit 0 Bit 1 Blue Bit 1 Bit 0 Blue Bit 0
As shown above, the 256 color pixel is divided into three parts: three bits for red, three bits for green, and two bits for blue. The red bits represent an index into the red LUT, the green bits represent an index into the green LUT, and the blue bits represent an index into the blue LUT. Although eight bitper-pixel only makes sense for a color panel, this memory model can be set on a monochrome panel, however only eight shades of gray will be visible.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 14
Epson Research and Development Vancouver Design Center
3.2.5 Memory Organization for 15 Bit-per-pixel (32768 Colors)
One pixel is stored in two bytes of display buffer as shown below: Table 3-5: Pixel Storage for 15 bpp (32768 Colors) in Two Bytes of Display Buffer
Bit 15 Reserved Bit 7 Green Bit 2 Bit 14 Red Bit 4 Bit 6 Green Bit 1 Bit 13 Red Bit 3 Bit 5 Green Bit 0 Bit 12 Red Bit 2 Bit 4 Blue Bit 4 Bit 11 Red Bit 1 Bit 3 Blue Bit 3 Bit 10 Red Bit 0 Bit 2 Blue Bit 2 Bit 9 Green Bit 4 Bit 1 Blue Bit 1 Bit 8 Green Bit 3 Bit 0 Blue Bit 0
As shown above, the 32768 color pixel is divided into four parts: five bits for red, five bits for green, and five bits for blue and one reserved bit. The output bypasses the LUT and goes directly into the Frame Rate Modulator. Although 15 bit-per-pixel only make sense for a color panel, this memory model can be set on a monochrome panel, however only 16 shades of gray will be visible.
3.2.6 Memory Organization for 16 Bit-per-pixel (65536 Colors)
One pixel is stored in two bytes of display buffer as shown below: Table 3-6: Pixel Storage for 16 bpp (65536 Colors) in Two Bytes of Display Buffer
Bit 15 Red Bit 4 Bit 7 Green Bit 2 Bit 14 Red Bit 3 Bit 6 Green Bit 1 Bit 13 Red Bit 2 Bit 5 Green Bit 0 Bit 12 Red Bit 1 Bit 4 Blue Bit 4 Bit 11 Red Bit 0 Bit 3 Blue Bit 3 Bit 10 Green Bit 5 Bit 2 Blue Bit 2 Bit 9 Green Bit 4 Bit 1 Blue Bit 1 Bit 8 Green Bit 3 Bit 0 Blue Bit 0
As shown above, the 65536 color pixel is divided into three parts: five bits for red, six bits for green, and five bits for blue. The output bypasses the LUT and goes directly into the Frame Rate Modulator. Although 16 bit-per-pixel only make sense for a color panel, this memory model can be set on a monochrome panel, however only 16 shades of gray will be visible.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 15
3.3 Look-Up Table (LUT)
This section provides a description of the LUT registers, followed by a description of the color and gray shade LUTs and a discussion of the banks available in the 2 and 8 bit-per-pixel (bpp) modes. The SED1354 LUT is only used for the panel interface. The optional RAMDAC is used to determine the colors for the CRT. See Section 6, "CRT Considerations" on page 33.
3.3.1 Look-Up Table Registers
REG[24h] Look-Up Table Address Register n/a n/a RGB Index Bit 1 RGB Index Bit 0 LUT Address Bit 3 LUT Address Bit 2 LUT Address Bit 1 Read/Write LUT Address Bit 0
REG[26h] Look-Up Table Data Register n/a n/a n/a n/a LUT Data Bit 3 LUT Data Bit 2 LUT Data Bit 1
Read/Write LUT Data Bit 0 Read/Write Red Bank Select Bit 0 Blue Bank Select Bit 1 Blue Bank Select Bit 0 Green Bank Select Bit 1 Green Bank Select Bit 0
REG[27h] Look-Up Table Bank Register n/a n/a Red Bank Select Bit 1
The SED1354 LUT Registers are located at offsets 24h, 26h and 27h. They consist of a LUT address register, data register and bank register. Refer to the SED1354 Hardware Functional Specification document number X19A-A-002-xx for more details.
RGB Index Selects which LUT to program. If set for Auto-increment, it will start at the Red LUT of the Index selected. Then with consecutive writes/reads it will increment to Green, then Blue of the same index, it will then increment the index and start at the Red LUT again. Auto-increment algorithm: 1. Set RGB Index to 0 for Auto-increment, set LUT address to 0 (i.e. REG[24h]=00h). 2. While count < or = to (16*3), write data byte to REG[26h]. R, G or B Index select algorithm: 1. Set RGB Index to R(01b), G(10b), or B(11b), set LUT address to 0 (e.g. REG[24h]=10h). 2. While count < or = 16, write data byte to REG[26h], increment LUT address. LUT Address Selects start index of the LUT in which to read data from, or write data to. Bank select has no effect on the CPU read/write to the LUT. LUT Data 4-bit data value to write.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 16
Epson Research and Development Vancouver Design Center
Bank Select Bits LUT banks are provided to give the application developer a choice of colors/gray shades. While the chosen color depth (bpp) may limit the simultaneous colors available, the panel is capable of storing different combinations of colors in banks. This is useful when an application developer chooses to set Bank 0 to low intensity colors and set Bank 1 to high intensity. The application can easily switch between low intensity output and high intensity output by using one register write. Only two display modes support these bits: 2 bpp and 8 bpp. All other modes either bypass the LUT or have only Bank 0 starting at Index 00h. In 2 bpp mode, the 16 entry LUTs are logically split into 4 groups of 4 entries for each of R, G, B. Bank 0 = Indexes 00-03h Bank 1 = Indexes 04-07h Bank 2 = Indexes 08-0Bh Bank 3 = Indexes 0C-0Fh In 8 bpp mode, the 16 entry LUTs are logically split into 2 groups of 8 entries for both Red and Green as follows: Bank 0 = Indexes 00-07h Bank 1 = Indexes 08-0Fh For Blue the 16 entry LUT is logically split into 4 groups of 4 entries as follows: Bank 0 = Indexes 00-03h Bank 1 = Indexes 04-07h Bank 2 = Indexes 08-0Bh Bank 3 = Indexes 0C-0Fh The bank select bits only affect data output. CPU access to the LUT indexes are done directly as in the example below: To program index 3 of the current LUT, with Green bank select bits set to 11b and 2 bpp gray shade mode selected, you would program LUT address to [[3(bank select value)*4(entries in LUT]+3(index to modify)-1(to zero-base the value)]=14(0Eh).
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 17
3.3.2 Look-Up Table Organization
* The Look-Up Table (LUT) treats the value of a pixel as an index into an array of colors or gray shades. For example, a pixel value of zero would point to the first LUT entry; a pixel value of 7 would point to the eighth LUT entry. * The value inside each LUT entry represents the intensity of the given color or gray shade. This value ranges between 0 and 0Fh. * The SED1354 LUT is linear; increasing the LUT number results in a lighter color or gray shade. For example, a LUT entry of 0Fh into the red Look-Up entry will always result in a bright red output.
Table 3-7: Look-Up Table Configurations
Display Mode RED 1 bpp gray 2 bpp gray 4 bpp gray 8 bpp gray 15 bpp gray 16 bpp gray 1 bpp color 2 bpp color 4 bpp color 8 bpp color 15 bpp color 16 bpp color 1 bank of 2 4 banks of 4 1 bank of 16 2 banks of 8 1 bank of 2 4 banks of 4 1 bank of 16 2 banks of 8 1 bank of 2 4 banks of 4 1 bank of 16 4 banks of 4 4-Bit Wide Look-Up Table GREEN 1 bank of 2 4 banks of 4 1 bank of 16 2 banks of 8 BLUE 2 gray shades 4 gray shades 16 gray shades 8 gray shades 16 gray shades 16 gray shades 2 colors 4 colors 16 colors 256 colors 4096 colors* 4096 colors* Effective Grays/Colors on an Passive Panel
* On a TFT panel the effective colors are determined by the interface width. (i.e. 9-bit=512, 12-bit=4096, 18-bit=64K colors) Passive panels are limited to 12-bits (4096) through the frame rate modulator.
Indicates the look-up table is not used for that display mode
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 18
Epson Research and Development Vancouver Design Center
Color Modes In color mode, the SED1354 supports three, 16 position, 4 bit wide color LUTs (red, green, and blue). Depending on the selected pixel size, these LUTs will provide from 1 to 4 banks. 1 bpp Color In 1 bpp color mode, the LUT is limited to a single 2 entry bank per color. The LUT bank select bits have no effect in this mode. The following table shows the recommended values for obtaining a Black-and-White mode while on a color panel. Table 3-8: Recommended LUT Values for 1 bpp Color Mode
Address 00 01 02 03 04 05 06 07 Red 00 0F 00 00 00 00 00 00 Green 00 0F 00 00 00 00 00 00 Blue 00 0F 00 00 00 00 00 00 Address 08 09 0A 0B 0C 0D 0E 0F Red 00 00 00 00 00 00 00 00 Green 00 00 00 00 00 00 00 00 Blue 00 00 00 00 00 00 00 00
2 bpp Color In 2 bpp color mode, the 16 LUT entries are divided into four separate 4 entry banks per color. The following table demonstrates recommended LUT data values which produce Bank 0 = low intensity, Bank 1 = high intensity, Bank 2 = inverted low intensity, Bank 3 = inverted high intensity. Table 3-9: Recommended LUT Values for 2 bpp Color Mode
Address 00 01 02 03 04 05 06 07 Red 00 03 05 07 00 0A 0D 0F Green 00 03 05 07 00 0A 0D 0F Blue 00 03 05 07 00 0A 0D 0F Address 08 09 0A 0B 0C 0D 0E 0F Red 07 05 03 00 0F 0D 0A 00 Green 07 05 03 00 0F 0D 0A 00 Blue 07 05 03 00 0F 0D 0A 00
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 19
4 bpp Color In 4 bpp color mode, the LUT is limited to a single 16 entry bank per color. The LUT bank select bits have no effect in this mode. The following table is a recommended set of data values to simulate the 16 colors in a VGA. The second recommendation for this mode is to program the register values to data values equalling the register number. (i.e. R[0] = 0, G[0]=0, B[0]=0, R[1]=1 ... R[F]=0Fh ...) Table 3-10: Recommended LUT Values to Simulate VGA Default 16 Color Palette
Address 00 01 02 03 04 05 06 07 Red 00 00 00 00 0A 0A 0A 0A Green 00 00 0A 0A 00 00 0A 0A Blue 00 0A 00 0A 00 0A 00 0A Address 08 09 0A 0B 0C 0D 0E 0F Red 00 00 00 00 0F 0F 0F 0F Green 00 00 0F 0F 00 00 0F 0F Blue 00 0F 00 0F 00 0F 00 0F
8 bpp Color In 8 bpp color mode, pixel bits [7:5] represent the red LUT index, bits [4:2] represent the green LUT index, and bits [1:0] represent the blue LUT index. It is recommended that the three LUTs are programmed according to the following format: Table 3-11: Recommended LUT Values For 8 bpp Color Mode
Address 00 01 02 03 04 05 06 07 Red 00 03 05 07 09 0B 0D 0F Green 00 03 05 07 09 0B 0D 0F Blue 00 05 0A 0F bank 1 bank 1 bank 1 bank 1
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 20
Epson Research and Development Vancouver Design Center
This recommended palette assumes that you are using only bank 0 of the three color components. By programming in the above fashion the following colors will result: Table 3-12: Examples of 256 Pixel Colors Using Linear LUT
Pixel Value
(binary)
Color black dark blue dark green dark cyan dark red dark magenta dark yellow gray
Pixel Value
(binary)
Color black bright blue bright green bright cyan bright red bright magenta bright yellow white
000 000 00 000 000 10 000 100 00 000 100 10 100 000 00 100 000 10 100 100 00 100 100 10
000 000 00 000 000 11 000 111 00 000 111 11 111 000 00 111 000 11 111 111 00 111 111 11
15 bpp Color Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The colors on the display are derived from only the top 4 bits of each color combination. Resulting in a maximum of 212=4096 colors. 16 bpp Color Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The colors on the display are derived from only the top 4 bits of each color combination. Resulting in a maximum of 212=4096 colors. Gray Shade Modes In gray shade mode, the SED1354 treats the Green LUT as a 16 position, 4 bit wide monochrome LUT. Depending on the selected pixel size, this LUT will provide from 1 to 4 banks. 1 bpp Gray Shade The SED1354 has no true Black-and-White mode. 1 bpp Gray consists of a single bank of two entries. For Black-and-White mode, the LUT entry must be programmed as such: . Table 3-13: Recommended LUT Values for 1 bpp Gray Shades
Index
(hex)
Look-Up Table Data
(hex)
00 01
00 0F
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 21
2 bpp Gray Shade In 2 bpp gray shade mode, the 16 LUT entries are divided into four separate banks, each having four entries: Table 3-14: Recommended LUT Values for 2 bpp Gray Shades
Index
(hex)
Look-Up Table Data
(hex)
00 01 02 03
00 05 0A 0F
4 bpp Gray Shade In 4 bpp gray shade mode, the pixel value indexes into one of 16 LUT entries. The LUT bank bits are ignored in this mode. The recommendation for this mode is to program the register values to data values equalling the register number (i.e. G[0] = 0, G[1]=1, G[2]=2, ... G[F]=0Fh). 8 bpp Gray Shade When the SED1354 is configured for 8 bpp gray shade mode, bits [7:5] are ignored, bits [4:2] represent the green LUT index, and bits [1:0] are ignored. Only 3 bits of the 8 that actually represent any shade value, therefore the maximum gray shade combination is 8 shades. If this limitation is deemed appropriate for your application, it is recommended that the LUTs are programmed according to the following format: Red and Blue LUT entries are not important, Green LUT indexes 0-7 should be programmed 0-F as in the table below: Table 3-15: Recommended LUT Values for 8 bpp Gray Shade
LUT Address 00 01 02 03 04 05 06 07 Green LUT Data 00 02 04 06 08 0A 0C 0F
This recommended LUT assumes that you are using only bank 0.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 22
Epson Research and Development Vancouver Design Center
15 bpp Gray Shade Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data. Resulting in a maximum of 24=16 colors. 16 bpp Gray Shade Since the Look-Up Table is bypassed in this mode, the LUT programming is unimportant. The gray shades on the display are derived from the 4 most significant bits of the Green component of the pixel data. Resulting in a maximum of 24=16 colors.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 23
4 Advanced Techniques
This section presents information on the following: * virtual display * panning and scrolling * split screen display
4.1 Virtual Display
A virtual display is when the image to be displayed is larger than the physical display device in either the horizontal dimension, the vertical dimension, or both. To view the image, the physical display is used as a window or viewport into the display buffer, allowing the user to see a portion of the entire image. This viewport can be panned and scrolled, enabling the user to view the entire image. The size of the virtual display is limited by the amount of available display buffer. In the case of an SED1354 with 2M byte of display buffer, the maximum virtual width ranges from 16,368 pixels in 1 bpp mode to 1023 pixels in 16 bpp mode. The maximum vertical size at the horizontal maximum is 1025 lines. By trading off horizontal size a greater vertical size can be achieved. Seldom are the maximum sizes required. Figure 4-1: "Viewport Inside a Virtual Display," depicts a more typical use of a virtual display. An image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling.
320x240 Viewport 640x480 "Virtual" Display
Figure 4-1: Viewport Inside a Virtual Display
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 24
Epson Research and Development Vancouver Design Center
4.1.1 Registers
REG[16h] Memory Address Offset Register 0 Memory Address Offset Bit 7 Memory Address Offset Bit 6 Memory Address Offset Bit 5 Memory Address Offset Bit 4 Memory Address Offset Bit 3 Memory Address Offset Bit 2 Memory Address Offset Bit 1 Memory Address Offset Bit 0
REG[17h] Memory Address Offset Register 1 n/a n/a n/a n/a n/a n/a Memory Address Offset Bit 9 Memory Address Offset Bit 8
Registers [16h] and [17h] form a ten bit value referred to as the memory offset. This offset is the number of words from the first byte of one line of display buffer to the first byte in the next line. This value takes into account the number of non-displayed pixels on each line. Different color depths have different numbers of pixels per word. To represent an offset of a given number of pixels the offset registers will contain different values at different color depths. The formula to calculate the offset to write to these registers is: offset_register = pixels_per_line / pixels_per_word
4.1.2 Examples
Example 2: Determine the offset value required for 800 pixels at a color depth of 8 bpp.
A color depth of 8 bpp means each pixel requires one byte therefore each word contains two pixels. offset = pixels_per_line / pixels_per_word = 800 / 2 = 400 = 0x190 words Register [17h] would be set to 0x01 and register [16h] would be set to 0x90.
Example 3: Program the Memory Address Offset Registers to support a 16 color (4 bpp) 640x480 virtual display on a 320x240 LCD panel.
To create a virtual display the offset registers must be programmed to the horizontal size of the larger "virtual" image. After determining the amount of memory used by each line, do a calculation to see if there is enough memory to support the desired number of lines. 1. 2. Initialize the SED1354 registers for a 320x240 panel. (See Section 2.2, "Register Initialization" on page 9). Determine the number of words required per line (the offset). In this case we want a width of 640 pixels and there are four pixels to every word. offset = pixels_per_line / pixels_per_word = 640 / 4 = 160 words = 0xA0 words 3. Check that we have enough memory for the required virtual height. Each line uses 160 words and we need 480 lines (160*480) for a total of 76,800 words, less than the minimum supported memory size of 512K bytes. It is safe to continue with these values.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 25
4.
Program the Memory Address Offset Registers. Register [17h] will be set to 0 and register [16h] will be set to 0xA0.
4.2 Panning and Scrolling
Panning and scrolling are typically used to navigate within an image which is too large to be shown completely on the display device. Although the image is stored entirely in display buffer, only a portion is actually visible at any given time. Panning and scrolling refers to the direction the viewport appears to move. Panning describes the action where the viewport moves horizontally. When panning to the right the image in the viewport appears to slide to the left. A pan to the left causes the image to appear as if it's sliding to the right. Scrolling describes the up and down motion of the viewport. Scrolling down causes the image to appear to slide upwards and scrolling up results in an image that appears to slide downwards. On the SED1354 panning is performed by setting two components: the start address registers provide a word granularity in movement (more than one pixel) while the pixel panning register allows panning at the pixel level. Scrolling requires changing only the start address registers. There is an order these registers should be accessed to provide the smoothest apparent movement possible. Understanding the sequence of operations performed by the SED1354 will make it apparent why the order should be followed. The start address is latched at the beginning of each frame, the pixel panning value is latched immediately upon being set. Setting the registers in the wrong sequence or at the wrong time will result in a "tearing" or jitter on the display. The correct sequence for programing these registers is: 1. 2. 3. 4. Wait until just after a vertical non-display period (read register [0Ah] and watch bit 7 for the non-display status). Update the start address registers. Wait until the next vertical non-display period. Update the pixel paning register.
Note The SED1354 provides a false indication of vertical non-display period when used with a dual panel display. In this case it is impossible to identify the false signal from the true non-display period. The result is that panning operations at less than 15 bpp may exhibit an occasional tear as the result of updating registers in the wrong order. This effect is barely noticeable at 8 bpp but becomes pronounced at 4 bpp, and lower, color depths. Setting the registers out of sequence will make the tear more apparent.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 26
Epson Research and Development Vancouver Design Center
4.2.1 Registers
REG[10h] Screen 1 Display Start Address 0 Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 REG[11h] Screen 1 Display Start Address 1 Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 REG[12h] Screen 1 Display Start Address 2 n/a n/a n/a n/a Start Address Bit 19 Start Address Bit 18 Start Address Bit 17 Start Address Bit 16 Start Address Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 Start Address Bit 8 Start Address Bit 4 Start Address Bit 3 Start Address Start Address Start Address Bit 2 Bit 1 Bit 0
These three registers form the address of the word in the display buffer where screen 1 will start displaying from. Changing these registers by one will cause a change of 0 to 16 pixels depending on the current color depth. Refer to the following table to see the minimum number of pixels affected by a change of one to these registers. Table 4-1: Number of Pixels Panned Using Start Address
Color Depth (bpp) 1 2 4 8 15 16 Pixels per Word 16 8 4 2 1 1 Number of Pixels Panned 16 8 4 2 1 1
REG[18h] Pixel Panning Register Screen 2 Pixel Pan Bit 3 Screen 2 Pixel Pan Bit 2 Screen 2 Pixel Pan Bit 1 Screen 2 Pixel Pan Bit 0 Screen 1 Pixel Pan Bit 3 Screen 1 Pixel Pan Bit 2 Screen 1 Pixel Pan Bit 1 Screen 1 Pixel Pan Bit 0
The pixel panning register offers finer control over pixel pans than is available with the Start Address Registers. Using this register it is possible to pan the displayed image one pixel at a time. Depending on the current color depth certain bits of the pixel pan register are not used. The following table shows this. Table 4-2: Active Pixel Pan Bits
Color Depth (bpp) 1 2 4 8 15/16 Pixel Pan bits used bits [3:0] bits [2:0] bits [1:0] bit 0 ---
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 27
4.2.2 Examples
For the examples in this section assume that the display system has been set up to view a 640x480 pixel image in a 320x200 viewport. Refer to Section 2.2, "Register Initialization" on page 9 and Section 4.1, "Virtual Display" on page 23 for assistance with these settings.
Example 4: Panning - Right and Left
To pan to the right, increment the pixel pan value. If the pixel pan value is now equal to the current color depth then set the pixel pan value to zero and increment the start address value. To pan to the left decrement the pixel pan value. If the pixel pan value is now less than zero set it to the color depth (bpp) less one and decrement the start address value. The following pans to the right by one pixel in 4 bpp display mode. 1. 2. It's better to keep one value (call it pan_value) to track both the pixel panning and start address rather than maintain separate values for each of these. To pan to the right increment pan_value. pan_value = pan_value + 1 3. Mask off the values from pan_value for the pixel panning and start address register portions. In this case, 4 bpp, the lower two bits are the pixel panning value and the upper bits are the start address. pixel_pan = pan_value AND 3 start_address = pan_value SHR 3 4. (shift right by 3 gives words)
Write the pixel panning and start address values to their respective registers using the procedure outlined in the registers section.
Example 5: Scrolling - Up and Down
To scroll down, increase the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line. To scroll up, decrease the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line.
Example 6: Scroll down one line for a 16 color 640x480 virtual image using a 320x240 single panel LCD.
1.
To scroll down we need to know how many words each line takes up. At sixteen colors (4 bpp) each byte contains two pixels so each word contains 4 pixels. words (offset) = pixels_per_line / pixels_per_word = 640 / 4 = 160 = 0xA0 We now know how much to add to the start address to scroll down one line.
2.
Increment the start address by the number of words per virtual line. start_address = start_address + words
3.
Separate the start address value into three bytes. Write the LSB to register [10h] and the MSB to register [12h].
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 28
Epson Research and Development Vancouver Design Center
4.3 Split Screen
Occasionally the need arises to display two distinct images on the display. For example, we may want to write a game where the main play area will be rapidly updated and we want an unchanging status display at the bottom of the screen. The Split Screen feature of the SED1354 allows a programmer to set up a display for such an application. The figure below illustrates setting up a 320x240 panel to have Image 1 displaying from scan line 0 to scan line 99 and image 2 displaying from scan line 100 to scan line 239. Although this example picks specific values, image 1 and image 2 can be shown as varying portions of the screen.
Scan Line 0 ... Scan Line 99 Scan Line 100 ... Scan Line 239 Screen 1 Display Line Count Register = 99 lines Figure 4-2: 320x240 Single Panel For Split Screen Image 1
Image 2
4.3.1 Registers
The other registers required for split screen operations, [10h] through [12h] (Screen 1 Display Start Address) and [18h] (Pixel Panning Register), are described in section 4.2.1 on page 26.
REG[0E] Screen 1 Line Compare Register 0 Line Line Line Line Line Line Line Line Compare Bit 7 Compare Bit 6 Compare Bit 5 Compare Bit 4 Compare Bit 3 Compare Bit 2 Compare Bit 1 Compare Bit 0 REG[0F] Screen 1 Line Compare Register 1 n/a n/a n/a n/a n/a n/a Line Line Compare Bit 9 Compare Bit 8
These two registers form a value known as the line compare. When the line compare value is equal to or greater than the physical number of lines being displayed there is no visible effect on the display. When the line compare value is less than the number of physically displayed lines, display operation works like this: 1. 2. From the end of vertical non-display to the number of lines indicated by line compare the display data will be from the memory pointed to by the Screen 1 Display Start Address. After line compare lines have been displayed the display will begin showing data from Screen 2 Display Start Address memory.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 29
REG[13h] Screen 2 Display Start Address Register 0 Start Address Bit 7 Start Address Bit 6 Start Address Bit 5 Start Address Bit 4 Start Address Bit 3 Start Address Bit 2 Start Address Bit 1 Start Address Bit 0
REG[14h] Screen 2 Display Start Address Register 1 Start Address Bit 15 Start Address Bit 14 Start Address Bit 13 Start Address Bit 12 Start Address Bit 11 Start Address Bit 10 Start Address Bit 9 Start Address Bit 8
REG[15h] Screen 2 Display Start Address Register 2 n/a n/a n/a n/a Start Address Bit 19 Start Address Bit 18 Start Address Bit 17 Start Address Bit 16
These three registers form the twenty bit offset to the first word in display buffer that will be shown in the screen 2 portion of the display. Screen 1 memory is always the first memory displayed at the top of the screen followed by screen 2 memory. However, the start address for the screen 2 image may in fact be lower in memory than that of screen 1 (i.e. screen 2 could be coming from offset 0 in the display buffer while screen 1 was coming from an offset located several thousand bytes into display buffer). While not particularly useful, it is possible to set screen 1 and screen 2 to the same address.
4.3.2 Examples
Example 7: Display 380 scanlines of image 1 and 100 scanlines of image 2. Image 2 is located immediately after image 1 in the display buffer. Assume a 640x480 display and a color depth of 1 bpp.
1.
The value for the line compare is not dependent on any other setting so we can set it immediately (380 = 0x17C). Write the line compare registers [0Fh] with 0x01 and register [0Eh] with 0x7C.
2.
Screen 1 is coming from offset 0 in the display buffer. Although not necessary, ensure that the screen 1 start address is set to zero. Write 0x00 to registers [10h], [11h] and [12h].
3.
Calculate the size of the screen 1 image (so we know where the screen 2 image is located). This calculation must be performed on the virtual size (offset register). Since a virtual size was not specified assume the virtual size to be the same as the physical size. offset = pixels_per_line / pixels_per_word = 640 / 16 = 40 words per line screen1_size = offset * lines = 40 * 480 = 19,200 words = 0x4B00 words
4.
Set the screen 2 start address to the value we just calculated. Write the screen 2 start address registers [13h], [14h] and [15h] with the values 0x00, 0x4B and 0x00 respectively.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 30
Epson Research and Development Vancouver Design Center
5 LCD Power Sequencing and Power Save Modes
5.1 Introduction to LCD Power Sequencing
LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD signals. Power sequencing is required to prevent long term damage to the panel and to avoid unsightly "lines" on power down and start-up. LCD Power Sequencing is performed on the SED1354 through a software procedure even when using hardware power save modes. Most "green" systems today use some sort of software power down procedure in conjunction with external circuitry to set hardware suspend modes. These procedures typically save/restore state information, or provide a timer prior to initiating power down. The SED1354 requires a timer between the time the LCD power is disabled and the time the LCD signals are shut down. Conversely, the LCD signals must be active prior to the power supply starting up. For simplicity, we have chosen to use the same time value for power up and power down procedures. The time interval required varies depending on the power supply design. The power supply on the SDU1354B0C Evaluation board requires 0.5 seconds to fully discharge. Your power supply design may vary. Below are the procedures for all cases in which power sequencing is required.
5.2 Introduction to Power Save Modes
The SED1354 has two power save modes. One is hardware-initiated via the SUSPEND# pin, the other is software-initiated through REG[1A] bit 0. Both require power sequencing as described above.
5.3 Registers
Register bits discussed in this section are highlighted.
Display Mode Register REG[0D] n/a Simultaneous Display Option Select Bit 1 Simultaneous Number of Display BPP Select Option Select Bit 2 Bit 0 Number of BPP Select Bit 1 Number of BPP Select Bit 0 CRT Enable LCD Enable
Power Save Configuration Register REG[1A] n/a n/a n/a n/a LCD Power Disable Suspend Refresh Select Bit 1 Suspend Refresh Select Bit 0 Software Suspend Mode Enable
Suspend Refresh Select bits [1:0] should be set on power up depending on the type of DRAM available. See the Hardware Functional Specification, document number X19A-A-002-xx.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 31
All other bits should be masked into the register on a write. i.e. do a read, modify with mask, and write to set the bits.
5.4 Suspend Sequencing
Care must be taken when enabling Suspend Mode with respect to the external Power Supply used to provide the LCD Drive voltage. The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage. Controlling the LCD Drive Power Supply can be done using the SED1354 LCDPWR# output signal or by 'other' means. The following example assumes that the LCDPWR# pin is being used.
5.4.1 Suspend Enable Sequence
Enable Suspend (Software Suspend= REG[1A] bit 0=1) or (Hardware Suspend enabled by the SUSPEND# input pin (MA9=0)): LCDPWR# will go to its inactive state within one vertical frame, while maintaining the LCD interface signals for 128 Vertical Frames (with the exception of FPFRAME(#?) which goes inactive at the same time as LCDPWR#). If 128 frames is not enough 'time' to allow the LCD Drive power supply to decay to 0V, LCDPWR# can be controlled manually using REG[1A] bit 3. After the 128 frame delay, the various clock sources may be disabled (depending on the specific application and DRAM Refresh options). The actual 'time' for the 128 frame delay can be shortened by using the following example. Shortening the 128 Frame delay using Software Suspend 1. Disable the Display FIFO: blank the screen. 2. Change the Horizontal and Vertical resolution to the minimum values allowed by the registers. 3. Enable Software Suspend: this same 128 frame delay still applies however the actual frame period is now greatly reduced. 4. Restore the Horizontal and Vertical resolution registers to their original values. 5. Disable Software Suspend. 6. Enable the Display FIFO. Shortening the 128 Frame Delay using Hardware SUSPEND# Due to the fact that the registers can not be programmed in Hardware Suspend Mode, the following routine must be followed to shorten the delay: 1. Disable the Display FIFO: blank the screen. 2. Change the Horizontal and Vertical resolutions to the minimum values as allowed by the registers.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 32
Epson Research and Development Vancouver Design Center
3. Enable Hardware Suspend: this same 128 frame delay still applies however the actual frame period is now greatly reduced. 4. Disable Hardware Suspend. 5. Restore the Horzontal and Vertical resolution registers to their original values. 6. Enable the Display FIFO.
5.4.2 Suspend Disable Sequence
Disable Suspend (either {REG[1A] bit 0 = 0, or SUSPEND# pin inactive): LCDPWR# and FPFRAME will start within 1 frame, while the remaining LCD interface signals will start immediately.
5.5 LCD Enable/Disable Sequencing (Reg[0D] bit 0)
In an LCD only product, the LCD Enable bit should only be disabled automatically by using a Power Save Mode. In a product having both a CRT and LCD, this bit will need to be controlled manually - examples for both situations are given below. LCD Enable / Disable using Power Save Modes In all supported Power Save Modes, the LCD Enable bit and associated functionality is automatically controlled by the internal Power Save circuitry. See above for Power Save sequences. LCD Enable / Disable using Manual Control It may become necessary to enable / disable the LCD when switching back and forth to and from the CRT. In this case care must be taken when disabling the LCD with respect to the external Power Supply used to provide the LCD Drive voltage. The LCD Drive voltage must be 0V before removing the LCD interface signals to prevent panel damage. Enable Setting REG[0D] bit 0=1: immediately enables the LCD interface signals. Note: FPLINE, FPSHIFT2/DRY signals are always toggling regardless of the state of this bit and are only shutdown completely during Power Save Modes. The LCDPWR# pin will go to its active state immediately after the LCD Enable bit is set. Disable Setting REG[0D] bit 0=0: LCDPWR# will go to its inactive state within one vertical frame, while maintaining the LCD interface signals for 128 Vertical Frames (with the exception of FPFRAME which goes inactive at the same time as LCDPWR#). If 128 frames is not enough 'time' to allow the LCD Drive power supply to decay to 0V, LCDPWR# can be controlled manually using REG[1A] bit 3.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 33
6 CRT Considerations
6.1 Introduction
The CRT timing is based on both the "VESA Monitor Timing Standards Version 1.0" and "Frame Rate Calculation (Chapter 11)" in SED1354 Hardware Functional Specification. The following sections describe CRT considerations.
6.1.1 CRT Only
For CRT only, the Dual/Single Panel Select bit of Panel Type Register (REG[02h]) must first be set to single passive LCD panel. The monitor configuration registers then need to be set to follow the VESA timing standard. Note If only the CRT is used, it is also useful to disable the LCD power (set REG[1Ah] bit 4 = 1). This will reduce power consumption. To program the external RAMDAC, set the CRT Enable bit in the Display Mode Register (REG[0Dh]) to 1. Once the CRT is enabled, the GPIO registers will be automatically set to access the external RAMDAC. Next, program the RAMDAC Write Mode Address register and the RAMDAC Palette Data register as desired (refer to sample code in 9.1.2 for details). When programming the RAMDAC control registers, connect the RAMDAC to the low-byte of the CPU data bus for Little-Endian architecture and the high-byte for Big-Endian architecture. The RAMDAC registers are mapped as follows: Table 6-1: RAMDAC Register Mapping for Little/Big-Endian
Register Name RAMDAC Pixel Read Mask RAMDAC Read Mode Address RAMDAC Write Mode Address RAMDAC Palette Data Little-Endian REG[28h] REG[2Ah] REG[2Ch] REG[2Eh] Big-Endian REG[29h] REG[2Bh] REG[2Dh] Reg[2Fh]
Note When accessing the External RAMDAC Control registers with either of the Little-Endian or Big-Endian architectures described above, accessing the adjacent unused registers is prohibited. Table 6-2 shows some example register data for setting up CRT only mode for certain combinations of resolutions, frame rates and pixel clocks. All the examples in this chapter are assumed to be for a Little-Endian system, 8 bpp color depth and 2M bytes of 60ns EDO-DRAM.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 34
Epson Research and Development Vancouver Design Center
Table 6-2: Related Register Data for CRT Only
Register REG[04h] REG[05h] REG[06h] REG[07h] REG[08h] REG[09h] REG[0Ah] REG[0Bh] REG[0Ch] REG[0Dh] REG[19h] REG[2Ch] REG[2Eh] 640X480@60Hz 640X480@75Hz 800X600@56Hz 800X600@60Hz
PCLK=25.175MHz PCLK=31.500MHz PCLK=36.0 MHz PCLK=40.0 MHz
Notes set horizontal display width set horizontal non-display period set HSYNC start position set HSYNC polarity and pulse width set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set VSYNC start position set VSYNC polarity and pulse width set 8 bpp and CRT enable set MCLK and PCLK divide set write mode address to 0 load RAMDAC palette data
0100 1111 0001 0011 0000 0001 0000 1011 1101 1111 0000 0001 0010 1100 0000 1001 0000 0001 0000 1110 0000 0000 0000 0000
0100 1111 0001 1000 0000 0001 0000 0111 1101 1111 0000 0001 0001 0011 0000 0000 0000 0010 0000 1110 0000 0000 0000 0000
0110 0011 0001 1011 0000 0010 1000 1000 0101 0111 0000 0010 0001 1000 0000 0000 1000 0001 0000 1110 0000 0000 0000 0000
0110 0011 0001 1111 0000 0100 1000 1111 0101 0111 0000 0010 0001 1011 0000 0000 1000 0011 0000 1110 0000 0000 0000 0000
6.1.2 Simultaneous Display
For Simultaneous Display, only 4/8-bit single passive LCD panels and 9-bit active matrix TFT panels can be used. Simultaneous Display requires that the panel timing be taken from the CRT timing registers and thereby limits the number of useful modes supported. The configuration of both CRT and panel must not violate the limitations as described in "Frame Rate Calculation" (Chapter 11) of the SED1354 Hardware Functional Specification. For example, on a 640x480 single panel, the maximum values of both the panel pixel clock and CRT frame rate are 40 MHz and 85 Hz respectively. When pixel depth is less than 8 bpp, the RAMDAC is programmed with the same values as the Look-Up Table. The SED1354 does not support Simultaneous Display in a color depth greater than 8 bpp. When color depth is 8 bpp, the RAMDAC should be programmed to mimic the recommended values in the Look-Up Table as described in Section 3.3.2. The recommendation is that the intensities of the three prime colors (RGB) be distributed evenly. Table 6-3 shows the recommended RAMDAC palette data for 8 bpp Simultaneous Display. Table 6-4 shows the related register data for some possible CRT options with an 8-bit Color 640X480 single passive panel.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 35
Table 6-3: 8 bpp Recommended RAMDAC palette data for Simultaneous Display
Address 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F Address 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F R 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 09 G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F Address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F R 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F Address 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F R 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B 1B G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 36
Epson Research and Development Vancouver Design Center
Addres s 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F
R 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24
G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F
B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F
Addres s A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF
R 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D 2D
G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F
B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F
Addres s C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
R 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36
G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F
B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F
Addres s E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
R 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F
G 00 00 00 00 09 09 09 09 12 12 12 12 1B 1B 1B 1B 24 24 24 24 2D 2D 2D 2D 36 36 36 36 3F 3F 3F 3F
B 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F 00 15 2A 3F
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 37
Table 6-4: Related register data for Simultaneous Display
Register REG[04h] REG[05h] REG[06h] REG[07h] REG[08h] REG[09h] REG[0Ah] REG[0Bh] REG[0Ch] REG[0Dh] REG[19h] REG[24h] REG[26h] REG[27h] REG[2Ch] REG[2Eh] 0000 0000 program RAMDAC 0000 0000 program RAMDAC 640X480@75Hz 640X480@60Hz
PCLK=40.0MHz PCLK=40.0MHz
Notes set horizontal display width set horizontal non-display period set HSYNC start position set HSYNC polarity and pulse width set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set VSYNC start position set VSYNC polarity and pulse width set 8 bpp and CRT enable set MCLK and PCLK divide set look-up table address to 0 load look-up table set look-up table to bank 0 set write mode address to 0 load RAMDAC palette data
0100 1111 0001 1101 0000 0011 0000 0111 1000 1111 0000 0001 0010 1100 0000 0000 1000 0010 0000 1111 0000 0000 0000 0000
0100 1111 0001 0011 0000 0001 0000 1011 1101 1111 0000 0001 0010 1100 0000 1001 0000 0001 0000 1111 0000 0000 0000 0000
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 38
Epson Research and Development Vancouver Design Center
7 Identifying the SED1354
Unlike previous generations of SED135x products, the SED1354 can be identified at any time after power-on/reset. The SED1354 and future SED135x products can be identified by reading REG[00h]. The value of this register for the SED1354F0A is 04h.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 39
8 Hardware Abstraction Layer (HAL)
8.1 Introduction
The HAL is a processor independent programming library provided by Seiko Epson. HAL provides an easy method to program and configure the SED1354. HAL allows easy porting from one SED135x product to another and between system architectures. HAL is included in the utilities provided with the SED1354 evaluation system.
8.2 API for 1354HAL
The following is a description of the HAL library. Updates and revisions to the HAL may include new functions not included in the following documentation
8.2.1 Initialization int seDeRegisterDevice(int device)
Description: Parameter: Removes a device's handle from the HAL library. device - registered device ID
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid
void seGetHalVersion(const char **pVersion, const char **pStatus, const char **pStatusRevision)
Description: Parameter: Gets HAL library version. pVersion - must point to an allocated string of size VER_SIZE pStatus - must point to an allocated string of size STATUS_SIZE pStatusRevision - must point to an allocated string of size STAT_REV_SIZE
Return Value: None
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 40
Epson Research and Development Vancouver Design Center
int seGetId(int device, BYTE *pId)
Description: Parameter: Reads the revision code register to determine the ID. device - registered device ID pId - pointer to allocated byte. The following are the possible values set to *pId: ID_SED1354F0A ID_SED1373F0A ID_SED1355F0A ID_UNKNOWN
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid Note seGetId() will disable hardware suspend (on the Intel platform only), and will enable the host interface (on all platforms).
int seInitHal(void)
Description: Initializes HAL library variables. Must be called once when application starts. (see note below). None
Parameter:
Return Value: ERR_OK - operation completed with no problems Note For Intel platforms, seRegisterDevice() automatically calls seInitHal() once. Consecutive calls to seRegisterDevice() will not call seInitHal() again. For embedded platforms, the startup code which is linked in addition to the HAL library will call seInitHal(). In this case, seInitHal() is called before main() is called in the application.
int seRegisterDevice(const DeviceInfoDef *pDeviceInfo, const DEVICE_CHIP_DEF *pDeviceChip, int *Device)
Description: Registers a device with the HAL library. The setup for the device is provided in the structures *pDeviceInfo and *pDeviceChip. In addition, it allocates memory addressing space for accessing registers and the display buffer. pDeviceInfo - pointer to HAL library structures pDeviceChip - pointer to HAL library structure dealing with chip specific features Device - pointer to an allocated INT. This routine will set *Device to the registered device ID.
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_STD_DEVICE - device argument is not HAL_STDOUT or HAL_STDIN Note No registers are actually changed by calling seRegisterDevice().
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 41
int seSetInit(int device)
Description: Sets the system to an operational state by initializing memory size, clocks, panel and CRT parameters,... etc. device - registered device ID
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid ERR_FAILED - unable to complete operation because registers have not been initialized
int seValidRegisteredDevice(int device)
Description: Parameter: Determines if the device handle is valid. device - registered device ID
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid
int seValidStdDevice(int device)
Description: Parameter: Determines if the device handle is HAL_STDOUT or HAL_STDIN. device - registered device ID
Return Value: ERR_OK - operation completed with no problems ERR_HAL_DEVICE_ERR - could not find free device handle
8.2.2 Screen Manipulation int seDisplayEnable(int device, BYTE NewState)
Description: Parameter: Performs the necessary power sequencing to enable or disable the display. device - registered device ID NewState - use the predefined definitions ENABLE and DISABLE.
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid ERR_FAILED - unable to complete operation because registers have not been initialized
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 42
Epson Research and Development Vancouver Design Center
int seGetBitsPerPixel(int device, BYTE *pBitsPerPixel)
Description: Parameter: Determines the color depth of current display mode. device - registered device ID pBitsPerPixel - if ERR_OK, *pBitsPerPixel set
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid ERR_COULD_NOT_GET_VALUE - value read from registers is invalid
int seGetBytesPerScanline(int device, int *pBytes)
Description: Determines the number of bytes per scan line of current display mode. It is assumed that the registers have already been correctly initialized before seGetBytesPerScanline() is called. device - registered device ID pBytes - pointer to an integer which indicates the number of bytes per scan line
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid
int seGetLastUsableByte(int device, DWORD *pLastByte)
Description: Determines the address of the last byte in the display buffer which can be used by applications. Addresses following LastByte are reserved for system use (such as the half frame buffer for dual panels). It is assumed that the registers have already been correctly initialized before seGetLastUsableByte() is called. device - registered device ID pLastByte - pointer to an integer which indicates the number of bytes per scan line
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid
int seGetLinearDispAddr(int device, DWORD *pDispLogicalAddr)
Description: Determines the logical address of the start of the display buffer. This address may be used in programs for direct control over the display buffer. device - registered device ID pDispLogicalAddr - logical address is returned in this variable.
Parameter:
Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 43
int seGetScreenSize(int device, int *width, int *height)
Description: Parameter: Determines the width and height of the active display device (LCD or CRT). device - registered device ID width - width of display in pixels height - height of display in pixels
Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
int seReadDisplayByte(int device, DWORD offset, BYTE *pByte)
Description: Parameter: Reads a byte from the display buffer. device - registered device ID offset - offset (in bytes) from start of the display buffer pByte - returns value of byte.
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seReadDisplayWord(int device, DWORD offset, WORD *pWord)
Description: Parameter: Reads a word from the display buffer. device - registered device ID offset - offset (in bytes) from start of the display buffer pWord - returns value of word.
Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
int seReadDisplayDword(int device, DWORD offset, DWORD *pDword)
Description: Parameter: Reads a dword from the display buffer. device - registered device ID offset - offset from start of the display buffer pDword - returns value of dword.
Return Value: ERR_OK - operation completed with no problems. ERR_INVALID_REG_DEVICE - device argument is not valid.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 44
Epson Research and Development Vancouver Design Center
int seSetBitsPerPixel(int device, BYTE BitsPerPixel)
Description: Parameter: Sets the number of bpp. This function is equivalent to a mode set. device - registered device ID BitsPerPixel - desired number of bpp
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_COULD_NOT_GET_VALUE - value read from registers is invalid. ERR_HAL_BAD_ARG - argument BitsPerPixel is invalid.
int seSplitInit(int device, DWORD Scrn1Addr, DWORD Scrn2Addr)
Description: Parameter: Sets the relevant registers for split screen. device - registered device ID Scrn1Addr - starting address of top image (addr = 0 refers to beginning of the display buffer) Scrn2Addr - starting address of bottom image (addr = 0 refers to beginning of the display buffer)
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. Note seSetInit() must first be called before calling seSplitInit(). This is because the VNDP is used for timing, and this would not be possible if the registers were not first initialized.
int seSplitScreen(int device, BYTE WhichScreen, int VisibleScanlines)
Description: Parameter: Changes the relevant registers for moving the split screen up or down. device - registered device ID WhichScreen - Use one of the following definitions: SCREEN1 or SCREEN2. SCREEN1 is the top screen. VisibleScanlines - number of lines to show for the selected screen
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_HAL_BAD_ARG - argument VisibleScanlines is negative or is greater than vertical panel size. Note seSplitInit() must have been called once before calling seSplitScreen().
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 45
int seVirtInit(int device, int xVirt, long *yVirt)
Description: Creates a virtual display with the given horizontal size and determines the maximum number of available lines. device - registered device ID xVirt - horizontal size of virtual display in pixels. Must be greater or equal to physical size of display. yVirt - seVirtInit() calculates the maximum number of lines available for virtual display and returns value in yVirt.
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_HAL_BAD_ARG - argument xVirt is too large. Select xVirt such that the Memory Address Offset register does not exceed 0x3ff. The maximum allowable xVirt is 0x3ff * (16 / bpp). If bpp is 15, use the above equation with bpp = 16. Note seSetInit() must have been called before calling seVirtInit(). This is because the VNDP is used for timing, and this would not be possible if the registers were not first initialized.
int seVirtMove(int device, BYTE WhichScreen, int x, int y)
Description: Parameter: Pans or scrolls the virtual display. device - registered device ID WhichScreen - Use one of the following definitions: SCREEN1 or SCREEN2. SCREEN1 is the top screen. x - new starting X position in pixels y - new starting Y position in pixels
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_HAL_BAD_ARG - argument WhichScreen is not SCREEN1 or SCREEN2. - argument Y is too large. - bpp is invalid in HAL structure (this would occur if the application changed the registers directly instead of calling seSetBitsPerPixel()). Note seVirtInit() must have been called once before calling seVirtMove().
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 46
Epson Research and Development Vancouver Design Center
int seWriteDisplayBytes(int device, DWORD addr, BYTE val, DWORD count)
Description: Parameter: Writes one or more bytes to the display buffer. device - registered device ID addr - offset from start of the display buffer val - value to write count - number of bytes to write
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seWriteDisplayWords(int device, DWORD addr, WORD val, DWORD count)
Description: Parameter: Writes one or more words to the display buffer. device - registered device ID addr - offset from start of the display buffer val - value to write count - number of words to write
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seWriteDisplayDwords(int device, DWORD addr, DWORD val, DWORD count)
Description: Parameter: Writes one or more dwords to the display buffer. device - registered device ID addr - offset from start of the display buffer val - value to write count - number of dwords to write
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 47
8.2.3 Color Manipulation int seGetDac(int device, BYTE *pDac)
Description: Parameter: Reads the entire DAC into an array. device - registered device ID pDac - pointer to an array of BYTE dac[256][3] dac[x][0] == RED component dac[x][1] == GREEN component dac[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seGetDacEntry(int device, BYTE index, BYTE *pEntry)
Description: Parameter: Reads one DAC entry. device - registered device ID index - index to DAC entry (0 to 255) pEntry - pointer to an array of BYTE entry[3] entry[x][0] == RED component entry[x][1] == GREEN component entry[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seGetLut(int device, BYTE *pLut)
Description: Parameter: Reads the entire LUT into an array. device - registered device ID pLut - pointer to an array of BYTE lut[16][3] lut[x][0] == RED component lut[x][1] == GREEN component lut[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 48
Epson Research and Development Vancouver Design Center
int seGetLutEntry(int device, BYTE index, BYTE *pEntry);
Description: Parameter: Reads one LUT entry. device - registered device ID index - index to LUT entry (0 to 15) pEntry - pointer to an array of BYTE entry[3] entry[x][0] == RED component entry[x][1] == GREEN component entry[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seSetDac(int device, BYTE *pDac)
Description: Parameter: Writes the entire DAC from an array into the DAC registers. device - registered device ID pDac - pointer to an array of BYTE dac[256][3] dac[x][0] == RED component dac[x][1] == GREEN component dac[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seSetDacEntry(int device, BYTE index, BYTE *pEntry)
Description: Parameter: Writes one DAC entry. device - registered device ID index - index to DAC entry (0 to 255) pEntry - pointer to an array of BYTE entry[3] entry[x][0] == RED component entry[x][1] == GREEN component entry[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 49
int seSetLut(int device, BYTE *pLut)
Description: Parameter: Writes the entire LUT from an array into the LUT registers. device - registered device ID pLut - pointer to an array of BYTE lut[16][3] lut[x][0] == RED component lut[x][1] == GREEN component lut[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seSetLutEntry(int device, BYTE index, BYTE *pEntry)
Description: Parameter: Writes one LUT entry. device - registered device ID index - index to LUT entry (0 to 15) pEntry - pointer to an array of BYTE entry[3] entry[x][0] == RED component entry[x][1] == GREEN component entry[x][2] == BLUE component
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seGet15BppInfo(int device, unsigned *RedMask, unsigned *GreenMask, unsigned *BlueMask)
Description: Determines the bit fields for the red, green, and blue components of a 15 bpp stored in a WORD. device - registered device ID RedMask - all bits set to 1 are used by the red component. GreenMask - all bits set to 1 are used by the green component. BlueMask - all bits set to 1 are used by the blue component.
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 50
Epson Research and Development Vancouver Design Center
8.2.4 Drawing int seDrawLine(int device, int x1, int y1, int x2, int y2, DWORD color)
Description: Parameter: Draws a line on the display. device - registered device ID. (x1, y1) - top left corner of line (x2, y2) - bottom right corner of line (see note below) color - color of line - For 1, 2, 4, and 8 bpp, color refers to the pixel value which points to the respective LUT/DAC entry. - For 15 and 16 bpp, color refers to the pixel value which stores the red, green, and blue intensities within a WORD. Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. Note seDrawLine() only draws horizontal and vertical lines, and that the line drawn does not include the endpoint (x2, y2).
int seDrawText(int device, char *fmt, ...)
Description: For Intel platforms, draws text to standard output. For embedded platforms, draws text to terminal. device - registered device ID. fmt - identical to printf() formatting strings ... - identical to printf() arguments for formatting strings
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_INVALID_STD_DEVICE - device is not HAL_STDOUT or HAL_STDIN (but don't use HAL_STDIN for seDrawText()). Note seDrawText() currently doesn't write text to the display buffer.
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 51
int seFillRect(int device, int x1, int y1, int x2, int y2, DWORD color)
Description: Parameter: Draws a solid rectangle on the display. device - registered device ID (x1, y1) - top left corner of rectangle (x2, y2) - bottom right corner of rectangle (see note below) color - color of rectangle - For 1, 2, 4, and 8 bpp, color refers to the pixel value which points to the respective LUT/DAC entry. For 15 and 16 bpp, color refers to the pixel value which stores the red, green, and blue intensities within a WORD.
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. Note seFillRect() does not fill the rectangle's right and bottom sides.
int seGetchar(void)
Description: Parameter: Gets a character from platform (typically from a terminal). none
Return Value: Character returned from platform.
int sePutchar(int ch)
Description: Parameter: Writes a character to platform (typically to a terminal). ch - character to send to platform
Return Value: ERR_OK - operation completed with no problems ERR_FAILED - operation failed
int sePutc(int device, int ch)
Description: Parameter: Writes a character to platform (typically to a terminal). device - registered device ID ch - character to send to platform
Return Value: ERR_OK - operation completed with no problems ERR_FAILED - operation failed
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 52
Epson Research and Development Vancouver Design Center
int seSetPixel(int device, int x, int y, DWORD color)
Description: Parameter: Writes a pixel to the display buffer. device - Registered device ID x - horizontal coordinate of the pixel (starting from 0) y - vertical coordinate of the pixel (starting from 0) color - for 1,2,4,8 BPP: refers to index into LUT/DAC. For 15,16 BPP: defines color directly (not LUT/DAC index)
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
8.2.5 Register Manipulation int seGetReg(int device, int index, BYTE *pVal)
Description: Parameter: Reads a register value. device - registered device ID index - register index pVal - returns value of the register
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
int seSetReg(int device, int index, BYTE val)
Description: Parameter: Writes a register value. device - registered device ID index - register index val - value to write to the register
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid.
8.2.6 Miscellaneous int seDelay(int device, DWORD Seconds)
Description: Delays for the given amount of time. For non-Intel platforms, the 1354 registers must be initialized and the VNDP set active (the VNDP is used as the timer). device - registered device ID Seconds - delay time in seconds
Parameter:
Return Value: ERR_OK - operation completed with no problems ERR_INVALID_REG_DEVICE - device argument is not valid. ERR_FAILED - registers have not been initialized (for non-Intel platforms).
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 53
WORD seRotateByteLeft(BYTE val, BYTE bits)
Description: Parameter: Rotates the bits in "val" left as many times as stated in "bits". val - value to rotate bits - how many bits to rotate
Return Value: bits 15-8: non-zero if carry flag set bits 7-0: rotated byte
WORD seRotateByteRight(BYTE val, BYTE bits)
Description: Parameter: Rotates the bits in "val" right as many times as stated in "bits". val - value to rotate bits - how many bits to rotate
Return Value: bits 15-8: non-zero if carry flag set bits 7-0: rotated byte
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 54
Epson Research and Development Vancouver Design Center
9 Sample Code
9.1 Introduction
The following code samples demonstrate two approaches to initializing the SED1354 color graphics controller with/without using the 1354HAL API. These code samples are for example purposes only.
9.1.1 Sample code using 1354HAL API
/* **------------------------------------------------------------------------** ** Created 1998, Epson Research & Development ** Vancouver Design Centre ** Copyright (c) 1998 Epson Research and Development, Inc. ** All rights reserved. ** **------------------------------------------------------------------------*/ #include #include #include #include #include "hal.h" "appcfg.h"
/*--------------------------------------------------------------------------*/ void main(void) { BYTE ChipId; int Device; switch (seRegisterDevice(&Cfg.DeviceInfo[0], &Cfg.DeviceChip, &Device)) { case ERR_OK: break; case HAL_DEVICE_ERR: printf("ERROR: Too many devices registered.\n"); exit(1); default: printf("ERROR: Could not register SED1354 device.\n"); exit(1); } seGetId(Device, &ChipId);
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 55
if (ChipId != ID_SED1354F0A) { printf("ERROR: Did not detect SED1354.\n"); exit(1); } if (seSetInit(Device) != ERR_OK) { printf("ERROR: Could not initialize device.\n"); exit(1); } /*************************************************************************** * Fill 2M bytes of memory with 0xffffffff (white) * Note that 0x200000 == 2 M bytes. Divide by 4 for number of Dwords to fill ***************************************************************************/ seWriteDisplayDwords(Device, 0, 0xffffffff, 0x200000/4); exit(0); }
9.1.2 Sample code without using 1354HAL API
/* **=========================================================================== ** INIT1354.C - sample code demonstrating the initialization of the SED1354. ** Beta release 2.0 98-10-22 ** ** The code in this example will perform initialization to the following ** specification: ** ** - 320 x 240 single 8-bit color passive panel. ** - 75 Hz frame rate. ** - 8 BPP (256 colors). ** - 33 MHz input clock. ** - 2 MB of 60 ns FPM memory. ** ** *** This is sample code only! *** ** This means: ** 1) Generic C is used. I assume that pointers can access the ** relevant memory addresses (this is not always the case). ** i.e. using the 1354B0B card on an Intel 16 bit platform will require ** changes to use a DOS extender to access memory and registers. ** 2) Register setup is done with discreet writes rather than being ** table driven. This allows for clearer commenting. A real program ** would probably store the register settings in an array and loop ** through the array writing each element to a control register.
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 56
Epson Research and Development Vancouver Design Center
** 3) The pointer assignment for the register offset does not work on ** Intel 16 bit platforms. ** **--------------------------------------------------------------------------** Created 1998, Epson Research & Development ** Vancouver Design Centre ** Copyright (c) 1998 Epson Research and Development, Inc. ** All rights reserved. **--------------------------------------------------------------------------** ** $Header: $ ** ** $Revision: $ ** ** $Log: $ ** **=========================================================================== */ unsigned char LUT8[8*3] = { 0x00, 0x00, 0x00, 0x02, 0x02, 0x05, 0x04, 0x04, 0x0A, 0x06, 0x06, 0x0F, 0x09, 0x09, 0x00, 0x0B, 0x0B, 0x00, 0x0D, 0x0D, 0x00, 0x0F, 0x0F, 0x00, }; /* ** REGISTER_OFFSET points to the starting address of the SED1354 registers */ #define REGISTER_OFFSET ((unsigned char *) 0x1234) void main(void) { unsigned char * pRegs; unsigned char * pLUT; int idx; int rgb; pRegs = REGISTER_OFFSET; /* ** Initialize the chip. */ /* ** Step 1: Enable the host interface. ** ** Register 1B: Miscellaneous Disable - host interface enabled, half frame ** buffer enabled. */ *(pRegs + 0x1B) = 0x00; /* 0000 0000 */
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 57
/* ** Step 2: Disable the display FIFO */ *(pRegs + 0x23) = 0x80; /* ** Step 3: Set the memory type ** ** Register 1: Memory Configuration - 4 ms refresh, EDO */ *(pRegs + 0x01) = 0x30; /* 0011 0000 */ /* ** Step 4: Set the performance register ** ** Register 22: Performance Enhancement */ *(pRegs + 0x22) = 0x24; /* 0010 0100 */ /* ** Step 5: Set dual/single panel ** ** Register 2: Panel Type - 8-bit, format 2, color, single, passive. */ *(pRegs + 0x02) = 0x1C; /* 0001 1100 */ /* ** Step 6: Set the rest of the registers in order. */ /* ** Register 3: Mod Rate */ *(pRegs + 0x03) = 0x00; /* 0000 0000 */ /* ** Register 4: Horizontal Display Width (HDP) - 320 pixels ** (320 / 8) - 1 = 39t = 27h */ *(pRegs + 0x04) = 0x27; /* 0010 0111 */ /* ** Register 5: Horizontal Non-Display Period (HNDP) ** PCLK ** Frame Rate = ----------------------------** (HDP + HNDP) * (VDP + VNDP) ** ** 8,250,000 ** = ----------------------------** (320 + HNDP) * (240 + VNDP) ** ** HNDP and VNDP must be calculated such that the desired frame rate ** is achieved. */ *(pRegs + 0x05) = 0x0F; /* 0000 1111 */ /*
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 58
Epson Research and Development Vancouver Design Center
** Register 6: HRTC/FPLINE Start Position - applicable to CRT/TFT only. */ *(pRegs + 0x06) = 0x00; /* 0000 0000 */ /* ** Register 7: HRTC/FPLINE Pulse Width - applicable to CRT/TFT only. */ *(pRegs + 0x07) = 0x00; /* 0000 0000*/ /* ** Registers 8-9: Vertical Display Height (VDP) - 240 lines. ** 240 - 1 = 239t = 0xEF */ *(pRegs + 0x08) = 0xEF; /* 1110 1111 */ *(pRegs + 0x09) = 0x00; /* 0000 0000 */ /* ** Register A: Vertical Non-Display Period (VNDP) ** This register must be programed with register 5 (HNDP) ** to arrive at the frame rate closest to the desired ** frame rate. */ *(pRegs + 0x0A) = 0x01; /* 0000 0001 */ /* ** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only. */ *(pRegs + 0x0B) = 0x00; /* 0000 0000 */ /* ** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only. */ *(pRegs + 0x0C) = 0x00; /* 0000 0000 */ /* ** Registers E-F: Screen 1 Line Compare - unless setting up for ** split screen operation use 0x3FF. */ *(pRegs + 0x0E) = 0xFF; /* 1111 1111 */ *(pRegs + 0x0F) = 0x03; /* 0000 0011 */ /* ** Registers 10-12: Screen 1 Display Start Address - start at the ** first byte in display memory. */ *(pRegs + 0x10) = 0x00; /* 0000 0000 */ *(pRegs + 0x11) = 0x00; /* 0000 0000 */ *(pRegs + 0x12) = 0x00; /* 0000 0000 */ /* ** Register 13-15: Screen 2 Display Start Address - not applicable ** unless setting up for split screen operation. */ *(pRegs + 0x13) = 0x00; /* 0000 0000 */ *(pRegs + 0x14) = 0x00; /* 0000 0000 */ *(pRegs + 0x15) = 0x00; /* 0000 0000 */ /*
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 59
** Register 16-17: Memory Address Offset - this address represents the ** starting WORD. At 8BPP our 320 pixel width is 160 ** WORDS */ *(pRegs + 0x16) = 0xA0; /* 1010 0000 */ *(pRegs + 0x17) = 0x00; /* 0000 0000 */ /* ** Register 18: Pixel Panning */ *(pRegs + 0x18) = 0x00; /* 0000 0000 */ /* ** Register 19: Clock Configuration - In this case we must divide ** MCLK by 4 to arrive at the best frequency to set ** our desired panel frame rate. */ *(pRegs + 0x19) = 0x03; /* 0000 0011 */ /* ** Register 1A: Power Save Configuration - enable LCD power, CBR refresh, ** not suspended. */ *(pRegs + 0x1A) = 0x00; /* 0000 0000 */ /* ** Register 1C-1D: MD Configuration Readback - don't write anything to ** these registers. */ /* ** Register 1E-1F: General I/O Pins Configuration - these values ** may need to be changed according to your system */ *(pRegs + 0x1E) = 0x00; /* 0000 0000 */ *(pRegs + 0x1F) = 0x00; /* 0000 0000 */ /* ** Register 20-21: General I/O Pins Control - these values ** may need to be changed according to your system */ *(pRegs + 0x20) = 0x00; /* 0000 0000 */ *(pRegs + 0x21) = 0x00; /* 0000 0000 */ /* ** Registers 24-27: LUT control. ** For this example do a typical 8BPP LUT setup. ** In 8BPP mode only the first 8 red, first 8 green ** and first 4 blue values are used. ** ** Setup the pointer to the LUT data and reset the LUT index register. ** Then, loop writing each of the RGB LUT data elements. */ pLUT = LUT8; *(pRegs + 0x24) = 0; for (idx = 0; idx < 8; idx++)
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 60
Epson Research and Development Vancouver Design Center
{ for (rgb = 0; rgb < 3; rgb++) { *(pRegs + 0x26) = *pLUT; pLUT++; } } /* ** Registers 28-2E: RAMDAC - not used in this example. Programmed very ** similarly to the LUT but all 256 entries are used. */ /* ** Register 23: Performance Enhancement - display FIFO enabled, optimum ** performance. */ *(pRegs + 0x23) = 0x10; /* 0001 0000 */ /* ** Register D: Display Mode - 8 BPP, LCD enable. */ *(pRegs + 0x0D) = 0x0D; /* 0000 1101 */ }
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
Epson Research and Development Vancouver Design Center
Page 61
Appendix A Supported Panel Values
A.1 Supported Panel Values
The following tables show related register data for different panels. All the examples are based on 8 bpp, 40MHz pixel clock and 2M bytes of 60 ns EDO-DRAM.
Table 9-1: Passive Single Panel
Passive 4-Bit Single
320X240@60Hz Monochrome
Register
Passive 8-Bit Single
320X240@60Hz Color
Passive 8-Bit Single
640X480@60Hz Monochrome
Passive 8-Bit Single
640X480@60Hz Color
Passive 16-Bit Single
640X480@47Hz Color
Notes
REG[02h] 0000 0000 REG[03h] 0000 0000 REG[04h] 0010 0111 REG[05h] 0001 0000 REG[08h] 1110 1111 REG[09h] 0000 0000 REG[0Ah] 0000 0001 REG[0Dh] 0000 1101 REG[19h] 0000 0110 REG[24h] 0000 0000 REG[26h] load LUT REG[27h] 0000 0000
0001 0100 0000 0000 0010 0111 0001 0000 1110 1111 0000 0000 0000 0001 0000 1101 0000 0110 0000 0000 load LUT 0000 0000
0001 0000 0000 0000 0100 1111 0000 0101 1101 1111 0000 0001 0000 0001 0000 1101 0000 0001 0000 0000 load LUT 0000 0000
0001 0100 0000 0000 0100 1111 0000 0101 1101 1111 0000 0001 0000 0001 0000 1101 0000 0001 0000 0000 load LUT 0000 0000
0010 0100 0000 0000 0100 1111 0000 0101 1101 1111 0000 0001 0000 0001 0000 1101 0000 0001 0000 0000 load LUT 0000 0000
set panel type set MOD rate set horizontal display width set horizontal non-display period set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set 8 bpp and LCD enable set MCLK and PCLK divide set Look-Up Table address to 0 load Look-Up Table set Look-Up Table to bank 0
Table 9-2: Passive Dual Panel
Passive 8-Bit Dual
640X480@60Hz Monochrome
Register
Passive 8-Bit Dual
640X480@60Hz Color
Passive 16-Bit Dual
640X480@60Hz Color
Notes
REG[02h] REG[03h] REG[04h] REG[05h] REG[08h] REG[09h] REG[0Ah] REG[0Dh] REG[19h] REG[1Bh] REG[24h] REG[26h] REG[27h]
0001 0010 0000 0000 0100 1111 0000 0101 1110 1111 0000 0000 0000 0001 0000 1101 0000 0011 0000 0000 0000 0000 load LUT 0000 0000
0001 0110 0000 0000 0100 1111 0000 0101 1110 1111 0000 0000 0000 0001 0000 1101 0000 0011 0000 0000 0000 0000 load LUT 0000 0000
0010 0110 0000 0000 0100 1111 0000 0101 1110 1111 0000 0000 0000 0001 0000 1101 0000 0011 0000 0000 0000 0000 load LUT 0000 0000
set panel type set MOD rate set horizontal display width set horizontal non-display period set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set 8 bpp and LCD enable set MCLK and PCLK divide enable half frame buffer set Look-Up Table address to 0 load Look-Up Table set Look-Up Table to bank 0
Programming Notes and Examples Issue Date: 98/10/28
SED1354 X19A-G-002-06
Page 62
Epson Research and Development Vancouver Design Center
Table 9-3: TFT Panel
TFT 16-Bit Single
640X480@47Hz Color
Register REG[02h] REG[03h] REG[04h] REG[05h] REG[06h] REG[07h] REG[08h] REG[09h] REG[0Ah] REG[0Bh] REG[0Ch] REG[0Dh] REG[19h] REG[24h] REG[26h] REG[27h]
Notes set panel type set MOD rate set horizontal display width set horizontal non-display period set HSYNC start position set HSYNC polarity and pulse width set vertical display height bits 7-0 set vertical display height bits 9-8 set vertical non-display period set VSYNC start position set VSYNC polarity and pulse width set 8 bpp and LCD enable set MCLK and PCLK divide set Look-Up Table address to 0 load Look-Up Table set Look-Up Table to bank 0
0010 0101 0000 0000 0100 1111 0001 0011 0000 0110 0000 0111 1101 1111 0000 0001 0010 1101 0000 0000 0000 0010 0000 1101 0000 0001 0000 0000 load LUT 0000 0000
SED1354 X19A-G-002-06
Programming Notes and Examples Issue Date: 98/10/28
SED1354F0A Register Summary
REG[00h] REVISION CODE REGISTER 2 Product Code 0 0 0 0 0 1 Revision Code 0 0 Bit 15 Bit 14 Bit 13 R0 REG[11h] SCREEN 1 DISPLAY START ADDRESS REGISTER 1 Screen 1 Display Start Address Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 RW Screen 1 Display Start Address Bit 19 Bit 18 Bit 17 Bit 16 RW Bit 2 Bit 1 Bit 0 RW Bit 10 Bit 9 Bit 8 RW Screen 2 Display Start Address Bit 19 Bit 18 Bit 17 Bit 16 RW Bit 3 Bit 2 Bit 1 Bit 0 RW n/a n/a Memory Address Offset Bit 9 Bit 8 RW Screen 1 Pixel Panning Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 RW n/a n/a MCLK Divide PCLK Divide 8 Bit 1 Bit 0 RW
9 LCD Power Suspend Refresh Select Disable Bit 1 Bit 0
X19A-Q-001-03
RW REG[22h] PERFORMANCE ENHANCEMENT REGISTER 0 EDO Read/ Write Delay RC Timing 10 Bit 1 Bit 0
11 RAS# to RAS# Precharge Timing CAS# Delay Bit 1 Bit 0
1/0 n/a
RW reserved
REG[12h] SCREEN 1 DISPLAY START ADDRESS REGISTER 2 REG[01h] MEMORY CONFIGURATION REGISTER n/a1 Refresh Rate 4 Bit 2 Bit 1 Bit 0 n/a WE# Control 1/0 n/a RW FPM/EDO Memory RW Bit 7 Bit 6 Bit 5 n/a n/a n/a n/a
REG[23h] PERFORMANCE ENHANCEMENT REGISTER 1 Display FIFO Disable n/a n/a Display FIFO Threshold Bit 4 Bit 3 Bit 2 Bit 1
RW Bit 0 RW Look-Up Table Address Bit 3 Bit 2 Bit 1 Bit 0 RW
REG[13h] SCREEN 2 DISPLAY START ADDRESS REGISTER 0 REG[02h] PANEL TYPE REGISTER Panel Data Width n/a n/a Bit 1
5
REG[24h] LOOK-UP TABLE ADDRESS REGISTER n/a n/a RGB Index Bit 1 Bit 0
1/0
Screen 2 Display Start Address Bit 4 Bit 3
Bit 0
TFT/ Panel Data Color/Mono Dual/Single Passive Format Panel Select Panel Select Panel Select Select RW MOD Rate
REG[14h] SCREEN 2 DISPLAY START ADDRESS REGISTER 1 REG[03h] MOD RATE REGISTER n/a n/a Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Screen 2 Display Start Address Bit 15 Bit 0 REG[15h] SCREEN 2 DISPLAY START ADDRESS REGISTER 2 REG[04h] HORIZONTAL DISPLAY WIDTH REGISTER n/a Horizontal Display Width = 8(REG + 1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[16h] MEMORY ADDRESS OFFSET REGISTER 0 REG[05h] HORIZONTAL NON-DISPLAY PERIOD REGISTER n/a n/a n/a Horizontal Non-Display Period = 8(REG + 1) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[17h] MEMORY ADDRESS OFFSET REGISTER 1 REG[06h] HRTC/FPLINE START POSITION REGISTER n/a n/a n/a HRTC/FPLINE Start Position = 8(REG + 1) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[18h] PIXEL PANNING REGISTER REG[07h] HRTC/FPLINE PULSE WIDTH REGISTER HRTC Polarity FPLINE Polarity n/a n/a HRTC/FPLINE Pulse Width = 8(REG + 1) Bit 3 Bit 2 Bit 1 Bit 0 REG[19h] CLOCK CONFIGURATION REGISTER REG[08h] VERTICAL DISPLAY HEIGHT REGISTER 0 Vertical Display Height = (REG + 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[1Ah] POWER SAVE CONFIGURATION REGISTER REG[09h] VERTICAL DISPLAY HEIGHT REGISTER 1 n/a n/a n/a n/a n/a n/a Bit 9 RW Vertical Display Height Bit 8 REG[1Bh] MISCELLANIOUS DISABLE REGISTER REG[0Ah] VERTICAL NON-DISPLAY PERIOD REGISTER VNDP Status (RO) n/a Vertical Non-Display Period (VNDP) = (REG + 1) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG[1Ch] MD CONFIGURATION READBACK REGISTER 0 REG[0Bh] VRTC/FPFRAME START POSITION REGISTER n/a n/a VRTC/FPFRAME Start Position = (REG + 1) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RW n/a VRTC/FPFRAME Pulse Width = (REG + 1) Bit 2 Bit 1 Bit 0 RW Number Of Bits-Per-Pixel 7 Bit 2 Bit 1 Bit 0 RW Bit 3 Bit 2 Bit 1 Bit 0 RW n/a n/a Screen 1 Line Compare Bit 9 Bit 8 RW Bit 2 Bit 1 Bit 0 CRT Enable LCD Enable REG[1Eh] GENERAL IO PINS CONFIGURATION REGISTER 0 GPIO7 Pin IO Config GPIO6 Pin IO Config GPIO5 Pin IO Config GPIO4Pin IO Config GPIO3 Pin IO Config GPIO2 Pin IO Config GPIO1 Pin IO Config REG[1Dh] MD CONFIGURATION READBACK REGISTER 1 MD15 Status MD14 Status MD13 Status MD12 Status MD11 Status MD10 Status MD9 Status RW RW Host Interface Disable n/a n/a n/a n/a n/a n/a n/a n/a n/a n/a RW n/a n/a n/a RW Bit 3 Screen 2 Pixel Panning Bit 2 Bit 1 RW n/a n/a n/a n/a RW Bit 7 Bit 6 Bit 5 Memory Address Offset Bit 4 RW n/a n/a n/a n/a Bit 14 Bit 13 Bit 12 Bit 11
REG[26h] LOOK-UP TABLE DATA REGISTER n/a n/a n/a n/a Look-Up Table Data Bit 3 Bit 2 Bit 1
Bit 0 RW
REG[27h] LOOK-UP TABLE BANK SELECT REGISTER n/a n/a Red Bank Select Bit 1
3
Blue Bank Select Bit 1 Bit 0
Green Bank Select Bit 1 Bit 0 RW
Bit 0
REG[28h] OR REG[29h] Bit 7 Bit 6
RAMDAC PIXEL READ MASK REGISTER RAMDAC Data Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 RW
REG[2Ah] OR REG[2Bh] 3 RAMDAC READ MODE ADDRESS REGISTER RAMDAC Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0 RW
REG[2Ch] OR REG[2Dh] 3 RAMDAC WRITE MODE ADDRESS REGISTER RAMDAC Address Bit 7 Bit 6
3
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 RW
REG[2Eh] OR REG[2Fh] Bit 7 Bit 6
RAMDAC PALETTE DATA REGISTER RAMDAC Data Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Software Suspend RW Half Frame Buffer Disable RO
Notes 1 n/a bits should be written 0. reserved bits must be written 0 2 These bits are used to identify the SED1354 at power on / RESET. 3 When using Little-Endian the RAMDAC should be connected to the low byte of the CPU data bus and the lower register address given used. When using Big-Endian the RAMDAC should be connected to the high byte of the CPU data bus and the higher register address given used. 4 DRAM Refresh Rate Select Refresh Rate Bits [2:0] 000 001 CLKI Divide Amount 64 128 256 512 1024 2048 4096 8192 Refresh Rate for 33MHz CLKI 520 kHz 260 kHz 130 kHz 65 kHz 33 kHz 16 kHz 8 kHz 4 kHz DRAM Refresh Time/256 cycles 0.5 ms 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms 64 ms
MD7 Status MD6 Status MD5 Status MD4 Status MD3 Status MD2 Status MD1 Status MD0 Status RO MD8 Status RW GPIO0 Pin IO Config RW GPIO9 Pin IO Config GPIO8 Pin IO Config RW GPIO2 Pin IO Status GPIO1 Pin IO Status GPIO0 Pin IO Status RW GPIO9 Pin IO Status GPIO8 Pin IO Status
010 011 100 101 110 111
REG[0Ch] VRTC/FPFRAME PULSE WIDTH REGISTER VRTC Polarity FPFRAME Polarity n/a n/a
REG[0Dh] DISPLAY MODE REGISTER n/a Simultaneous Display 6 Option Select Bit 1 Bit 0
REG[1Fh] GENERAL IO PINS CONFIGURATION REGISTER 1 n/a n/a n/a n/a GPIO11 Pin GPIO10 Pin IO Config IO Config
5 Panel Data Width Selection Panel Data Width Bits [1:0] 00 01 10 11 Passive LCD Panel Data Width Size 4-bit 8-bit 16-bit Reserved TFT Panel Data Width Size 9-bit 12-bit 16-bit Reserved
REG[0Eh] SCREEN 1 LINE COMPARE REGISTER 0 Screen 1 Line Compare Bit 7 Bit 6 Bit 5 Bit 4
REG[20h] GENERAL IO PINS STATUS / CONTROL REGISTER 0 GPIO7 Pin IO Status GPIO6 Pin IO Status GPIO5 Pin IO Status GPIO4 Pin IO Status GPIO3 Pin IO Status
REG[0Fh] SCREEN 1 LINE COMPARE REGISTER 1 n/a n/a n/a n/a
REG[21h] GENERAL IO PINS STATUS / CONTROL REGISTER 1 GPO Control n/a n/a n/a GPIO11 Pin GPIO10 Pin IO Status IO Status
REG[10h] SCREEN 1 DISPLAY START ADDRESS REGISTER 0 Screen 1 Display Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Page 1
98/09/15
SED1354F0A Register Summary
6 Simultaneous Display Option Selection Simultaneous Display Option Select Bits [1:0] 00 01 10 11 7 Number of Bits per Pixel Selection Number Of Bits/Pixel Select Bits [2:0] 000 001 010 011 100 101 110-111 8 PCLK Divide Selection PCLK Divide Select Bits [1:0] 00 01 10 11 9 Suspend Refresh Selection Suspend Refresh Select Bits [1:0] 00 01 1x 10 Minimum Memory Timing Selection RC Timing Bits [1:0] 00 01 10 11 11 RAS Precharge Timing Select RAS Precharge Timing Bits [1:0] 00 01 10 11 RAS Precharge Width 2 MCLK 1.5 MCLK 1 MCLK Reserved Minimum Random Cycle Width 5 MCLK 4 MCLK 3 MCLK Reserved DRAM Refresh Type CBR Refresh Self-Refresh No Refresh MCLK/PCLK Frequency Ratio 1 2 3 4 Number of Bits/Pixel 1 2 4 8 15 16 Reserved Simultaneous Display Option Normal Line Doubling Interlace Even Scan Only
X19A-Q-001-03
Page 2
98/09/15
SED1354 Color Graphics LCD/CRT Controller
1354CFG.EXE Configuration Program
Document Number: X19A-B-001-03
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1354CFG.EXE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Program Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Script Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interactive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1354CFG Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Viewing 1354CFG Menu Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Making 1354CFG Menu Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Files Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Device Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 CRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Advanced Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Lookup Table (LUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Help Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Sample Program Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 5
List of Figures
Figure 1: 1354CFG Menu Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 2: 1354CFG Open File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 3: 1354CFG Files Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 4: 1354CFG View Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 5: 1354CFG Current Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 6: 1354CFG Advanced Configuration (Partial View of Screen) . . . . . . . . . . . . . . . . . . . . . 14 Figure 7: 1354CFG Device Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8: 1354CFG Panel Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9: 1354CFG Edit Panel Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 10: 1354CFG Panel Parameter Edit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 11: 1354CFG CRT Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12: 1354CFG Edit CRT Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13: 1354CFG CRT Parameter Edit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14: 1354CFG Advanced Memory Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 15: 1354CFG Edit Advanced Memory Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 16: 1354CFG Memory Parameter Edit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 17: 1354CFG Power Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 18: 1354CFG Edit Power Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 19: 1354CFG Power Parameter Edit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 20: 1354CFG LUT Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 21: 1354CFG Edit LUT Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 22: 1354CFG LUT Parameter Edit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 23: 1354CFG Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 24: 1354CFG Setup Parameter Edit For Register Location, Memory Location, and Memory Size.. . . . 27
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 7
1354CFG.EXE
1354CFG gives a software/hardware developer an easy way to modify panel types, modes, etc. for the SED1354 utilities without recompiling. Once the correct operating environment has been determined, the software/hardware developer can modify the source code manually for a permanent change. 1354CFG changes the hardware configuration setup for each of the 1354 utilities, as well as any program designed by a software/hardware developer using the Hardware Abstraction Layer (HAL) library. * 1354CFG runs in two modes: one mode reads script files and the other mode is interactive. * In the interactive mode, the 1354CFG DOS-based program uses an interface similar to Windows to present one menu for each configuration section. Each section has its own dialog box showing all of the relevant elements for that section. * 1354CFG reads the configuration from a specific EXE file for Intel platforms, and from a specific S9 file for non-Intel platforms. * 1354CFG can select all EXE files for configuration writes. * 1354CFG prints or displays the configuration setup. * 1354CFG supports scripts to quickly reprogram all files to a given configuration setup. The given configuration is defined in an INI file. * 1354CFG is designed to work with a given version of the configuration setup structure. If the structure is of a different version, an error message is displayed and the program exits.
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 8
Epson Research and Development Vancouver Design Center
Program Requirements
Video Controller Display Type BIOS DOS Program DOS Version Windows Program Windows DOS Box : Any VGA : LCD or CRT : Any manufacturer's VGA BIOS : Yes : 3.0 or greater : No
: Yes Windows DOS Full Screen : Yes, Windows 3.1x and Windows 95 OS/2 DOS Full Screen : Yes
Installation
Copy the following files to a directory that is in the DOS path on your hard drive: 1354CFG.EXE G032.EXE OBJCOPY.EXE Note G032.EXE and OBJCOPY.EXE are called by 1354CFG.EXE for non-Intel platforms. Neither program is intended to run independent of 1354CFG.
Usage
At the DOS Prompt, type 1354cfg. 1354cfg.exe [filename.exe script.ini] [/?]
Where:
filename.exe script.ini
is the 1354 utility to be modified is the list of HAL configuration changes (see See "Script Mode" on page 9) displays the usage screen runs 1354CFG in the interactive mode
/? no argument
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 9
Script Mode
In script mode, a file provides 1354CFG with all the information necessary to reconfigure the selected 1354 utility. Any changes which can be made by the interactive user interface can also be done by the script file. Note that it is not necessary to list all of the possible items in the script file. For example, if the script is only to change the panel resolution, the script would only have the following lines: ; ;File TEST.INI ; Panel.x = 640 Panel.y = 480 To use this script file on the 1354PLAY utility, type the following: 1354CFG 1354PLAY.EXE TEST.INI In this example, all of the other panel settings in the 1354 utility remain the same. In general, however, it is necessary to set several more panel parameters before the panel is properly configured. The full list of all the possible parameters to 1354CFG is included in the file 1354.INI.
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 10
Epson Research and Development Vancouver Design Center
Interactive Mode
1354CFG Menu Bar
Menu Bar
Figure 1: 1354CFG Menu Bar
1354CFG has four main menus: Files, View, Device, and Help. Menu contents can be viewed by using either the mouse or the keyboard.
Viewing 1354CFG Menu Contents
Mouse Move the on-screen arrow with the mouse and point at the desired menu. Click the left mouse button and the contents of the menu will be displayed. Keyboard Press: to select the Files menu. to select the View menu. to select the Device menu. to select the Help menu. <>, <>, or the highlighted letter in the menu to select a menu item.
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 11
Making 1354CFG Menu Selections
In 1354CFG, a selection is made by clicking the left mouse button, or by pressing the tab and arrow keys on the keyboard. In the example below, there are three ways to select and open 1354SHOW.EXE in the Files box in the Open File window (figure 2). Mouse * Click the left mouse button on 1354SHOW.EXE to highlight it in the Files box. Then click on the OK button. * Point to the file 1354SHOW.EXE with the arrow and click the left mouse button twice in rapid succession (double-clicking). Keyboard * Press to highlight the Files box (or press ). Press <> to highlight 1354SHOW.EXE. Press . All selections in 1354CFG can be made in one of the three ways listed above.
Figure 2: 1354CFG Open File
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 12
Epson Research and Development Vancouver Design Center
Files Menu
Figure 3: 1354CFG Files Menu
The Files menu contains these functions: * Open - reads the HAL configuration for a given utility. Note A utility must be opened before any other menu command can be executed. * Save - saves the current changes to the opened file. * Save As - saves a file to a different name and/or different location. * Save All - saves modifications to all 1354 files that are in the same directory as the file being saved. This function ensures that the display parameters are consistent. "Save All" is only available for utilities run on an Intel (EXE) platform. * Exit - exits the 1354CFG application.
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 13
View Menu
Figure 4: 1354CFG View Menu
The View menu displays the Current Configuration and the Advanced Configuration of an opened utility. In the Current or Advanced Configuration window, the configuration of an opened file can be viewed only, not edited. Configuration parameters must be edited in the Panel, CRT, Advanced Memory, Power Management, Look-Up Table, and Setup sub-menus in the Device menu. Some configuration parameters cannot be readily changed as they depend on several factors for consistency (eg. Frame Rate, Clock Divides etc.). Refer to the SED1354 "Functional Hardware Specification" manual, document number X19A-A-002-xx, and the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx for formulas and other information. Note Epson R&D Inc. cannot be held liable for damage done to the display as a result of software configuration errors. Cancel and Print commands are available in the Current/Advanced Configuration windows. Help is listed, but is not available for this version of 1354CFG.
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 14
Epson Research and Development Vancouver Design Center
Figure 5: 1354CFG Current Configuration
Figure 6: 1354CFG Advanced Configuration (Partial View of Screen)
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 15
Device Menu
Figure 7: 1354CFG Device Menu
The Device menu contains the following sub-menus where parameters for a SED1354 utility can be edited: * Panel * CRT * Advanced Memory * Power Management * Look-Up Table * Setup
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 16
Epson Research and Development Vancouver Design Center
Panel
Panel Setup When Panel is selected from the Device menu, the Panel Setup dialog box is displayed. To select a panel assignment, highlight it (in the example window below, "STN 4 Bit Mono Single 320x240" is highlighted) and click OK. If the highlighted panel assignment needs changes, click Edit and see the next section "Edit Panel Setup." Whenever a panel assignment is edited or selected in the Panel Setup dialog box, the setup is copied to Current Configuration. The editing is automatically performed on the current configuration. In addition to OK, Cancel, and Edit commands, a Help command is listed in the Panel Setup windows. In this version of 1354CFG, the Help files are unavailable.
Figure 8: 1354CFG Panel Setup
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 17
Edit Panel Setup When a selection is highlighted in the Panel Setup window and Edit is clicked, the Edit Panel Setup window is displayed. The Edit Panel Setup window lists parameters which can be edited, as shown below in Figure 9, "1354CFG Edit Panel Setup." In this example window, "X Resolution: 320 pixels" is highlighted.
Figure 9: 1354CFG Edit Panel Setup
Panel Parameter Edit When a selection is highlighted for editing in the Edit Panel Setup window and Edit is clicked, the Panel Parameter Edit window displays for parameter editing. See figure 10, "1354CFG Panel Parameter Edit" below. In this example window, "X Resolution: 320 pixels" can be edited.
Figure 10: 1354CFG Panel Parameter Edit
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 18
Epson Research and Development Vancouver Design Center
CRT
CRT Setup When CRT is selected from the Device menu, the CRT Setup window is displayed. To select a CRT assignment, highlight it (in the example window below, "CRT 640x400 @ 85Hz, CLKI=33.333MHz" is highlighted) and click OK. If the highlighted CRT assignment needs changes, click Edit and see the next section "Edit CRT Setup." Whenever a CRT assignment is edited or selected in the CRT Setup dialog box, the setup is copied to Current Configuration. The editing is automatically performed on the current configuration. In addition to OK, Cancel, and Edit commands, a Help command is listed in the CRT setup windows. In this version of 1354CFG, the Help files are unavailable.
Figure 11: 1354CFG CRT Setup
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 19
Edit CRT Setup When a selection is highlighted in the CRT Setup window and Edit is clicked, the Edit CRT Setup window is displayed. The Edit CRT Setup window lists parameters which can be edited, as shown below in Figure 12, "1354CFG Edit CRT Setup." In this example window, "Horiz Non-Display: 240 pixels" is highlighted.
Figure 12: 1354CFG Edit CRT Setup
CRT Parameter Edit When a selection is highlighted for editing in the Edit CRT Setup window and Edit is clicked, the CRT Parameter Edit window displays for parameter editing. See figure 13, "1354CFG CRT Parameter Edit" below. In this example window, "Horiz Non-Display: 240 pixels" can be edited.
Figure 13: 1354CFG CRT Parameter Edit
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 20
Epson Research and Development Vancouver Design Center
Advanced Memory
Memory Setup When Advanced Memory is selected from the Device menu, the Memory Setup dialog box is displayed. To select a memory assignment, highlight it ( in the example window below, "Memory Type 0" is highlighted) and click OK. If the highlighted memory assignment needs changes, click Edit and see the next section "Edit Memory Setup." Whenever a memory assignment is edited or selected in the Memory Setup dialog box, the setup is copied to Current Configuration. The editing is automatically performed on the current configuration. In addition to OK, Cancel, and Edit commands, a Help command is listed in the Memory setup windows. In this version of 1354CFG, the Help files are unavailable.
Figure 14: 1354CFG Advanced Memory Setup
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 21
Edit Advanced Memory Setup When a selection is highlighted in the Memory Setup window and Edit is clicked, the Edit Advanced Memory Setup window is displayed. The Edit Advanced Memory window lists parameters which can be edited, as shown below in Figure 15, "1354CFG Edit Advanced Memory Setup." In this example window, "Refresh Time: 4000 Cycles" is highlighted.
Figure 15: 1354CFG Edit Advanced Memory Setup
Memory Parameter Edit When a selection is highlighted for editing in the Edit Advanced Memory Setup window and Edit is clicked, the Memory Parameter Edit window is displayed for parameter editing. See figure 16, "1354CFG Memory Parameter Edit" below. In this example window, "Refresh Time: 4000 Cycles" can be edited.
Figure 16: 1354CFG Memory Parameter Edit
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 22
Epson Research and Development Vancouver Design Center
Power Management
Power Setup When Power Management is selected from the Device menu, the Power Setup dialog box is displayed. To select a power assignment, highlight it (in the example window below, "Power Type 0" is highlighted) and click OK. If the highlighted power assignment needs changes, click Edit and see the next section "Edit Power Setup." Whenever a power assignment is edited or selected in the Power Setup dialog box, the setup is copied to Current Configuration. The editing is automatically performed on the current configuration. In addition to OK, Cancel, and Edit commands, a Help command is listed in the Power setup windows. In this version of 1354CFG, the Help files are unavailable.
Figure 17: 1354CFG Power Setup
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 23
Edit Power Setup When a selection is highlighted in the Power Setup window and Edit is clicked, the Edit Power Setup window is displayed. The Edit Power Setup window lists parameters which can be edited, as shown below in Figure 18, "1354CFG Edit Power Setup." In this example window, "Suspend Refresh: CBR Refresh" is highlighted.
Figure 18: 1354CFG Edit Power Setup
Power Parameter Edit When a selection is highlighted for editing in the Edit Power Setup window and Edit is clicked, the Power Parameter Edit window displays for parameter editing. See figure 19, "1354CFG Power Parameter Edit" below. In this example window, "Suspend Refresh: CBR Refresh" can be edited.
Figure 19: 1354CFG Power Parameter Edit
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 24
Epson Research and Development Vancouver Design Center
Lookup Table (LUT)
LUT Setup When Lookup Table is selected from the Device menu, the LUT Setup dialog box is displayed. To select a LUT assignment, highlight it (in the example window below, "LUT Internal 4 Color" is highlighted) and click OK. If the highlighted LUT assignment needs changes, click Edit and see the next section "Edit LUT Setup." Whenever a LUT assignment is edited or selected in the LUT Setup dialog box, the setup is copied to Current Configuration. The editing is automatically performed on the current configuration. In addition to OK, Cancel, and Edit commands, a Help command is listed in the LUT setup windows. In this version of 1354CFG, the Help files are unavailable.
Figure 20: 1354CFG LUT Setup
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 25
Edit LUT Setup When a selection is highlighted in the LUT Setup window and Edit is clicked, the Edit LUT Setup window is displayed. The Edit LUT Setup window lists parameters which can be edited, as shown below in Figure 21, "1354CFG Edit LUT Setup." In this example window, "Bits Per Pixel: 2" is highlighted. Note A future release of 1354CFG will enable components in the lookup table palette to be edited. (For example, the red, green, and blue components of LUT palette entry 0Fh could be edited.)
Figure 21: 1354CFG Edit LUT Setup
LUT Parameter Edit When a selection is highlighted for editing in the Edit LUT Setup window and Edit is clicked, the LUT Parameter Edit window displays for parameter editing. See figure 22, "1354CFG LUT Parameter Edit" below. In this example window, "Bits Per Pixel: 2" can be edited.
Figure 22: 1354CFG LUT Parameter Edit
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 26
Epson Research and Development Vancouver Design Center
Setup
When Setup is selected from the Device menu, the Setup dialog box is displayed. To select either Register Location, Memory Location, or Memory Size, highlight it (in the example window below, "Register Location: 00C00000 (hex)" is highlighted) and click OK. If the highlighted Setup assignment needs changes, click Edit and see the next section "Setup Parameter Edit." In addition to OK, Cancel, and Edit commands, a Help command is listed in the Setup windows. In this version of 1354CFG, the Help files are unavailable.
Figure 23: 1354CFG Setup
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 27
Setup Parameter Edit When a selection is highlighted in the Setup window and Edit is clicked, a Setup Parameter Edit window is displayed for parameter editing. The Setup Parameter Edit windows for Register Location, Memory Location, and Memory Size respectively are shown below.
Figure 24: 1354CFG Setup Parameter Edit For Register Location, Memory Location, and Memory Size.
Help Menu
There are three files in the Help menu. * Help: not available in this version of 1354CFG. * Help on Help: not available in this version of 1354CFG. * About: displays copyright and program version information.
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 X19A-B-001-03
Page 28
Epson Research and Development Vancouver Design Center
Comments
It is assumed that the 1354CFG user is familiar with SED1354 hardware and software. Refer to the SED1354 "Functional Hardware Specification," document number X19A-A-002-xx, and the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx for information. In addition, the 1354CFG user must know the hardware setup for the panel and CRT, and the setup for the given hardware platform (such as memory addresses and memory speed).
Sample Program Messages
ERROR: Could not open . Could not open the 1354 utility called . This message is generated from the command line: 1354CFG filename script.ini. ILLEGAL VALUE: Choose between 8 and 800, in multiples of 8 pixels. The user entered an invalid number when changing the Panel X Resolution. ERROR: Failed to open the file! The selected program does not have the HAL structure, therefore cannot be opened by 1354CFG.
SED1354 X19A-B-001-03
1354CFG.EXE Configuration Program Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
1354SHOW Demonstration Program
Document Number: X19A-B-002-04
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-002-04
1354SHOW Demonstration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
1354SHOW
1354SHOW demonstrates SED1354 display capabilities by drawing a pattern image at different pixel depths (i.e. 16 bits-per-pixel, 2 bits-per-pixel, etc.) on the display. The 1354SHOW display utility must be configured and/or compiled to work with your hardware platform. Consult documentation for the program 1354CFG.EXE which can be used to configure 1354SHOW. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection.
SED1354 Supported Evaluation Platforms
1354SHOW has been tested with the following SED1354 supported evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx.
Installation
PC platform: copy the file 1354SHOW.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 1354SHOW to the system.
1354SHOW Demonstration Program Issue Date: 98/10/29
SED1354 X19A-B-002-04
Page 4
Epson Research and Development Vancouver Design Center
Usage
PC platform: at the prompt, type 1354show [b=??] [/a] [/lcd] [/crt] [/vertical] [/?]. Embedded platform: execute 1354show and at the prompt, type the command line argument.
Where:
b=?? /a /lcd /crt /vertical /? /noinit
starts 1354SHOW at a user specified bits-per-pixel (bpp) level, where ?? can be: 1, 2, 4, 8, 15, or 16 automatically cycles through all video modes displays on the LCD panel displays on the CRT displays vertical line pattern displays the help screen bypasses register initialization
Comments
* 1354SHOW cannot show a greater color depth than the display allows. * The PC must not have more than 12M bytes of system memory when used with the SDU1354B0C board. * Follow simultaneous display guidelines for correct simultaneous display operation. * To determine if the CRT will operate correctly when using a dual panel, refer to the "Maximum Frame Rates" table in the SED1354 "Functional Hardware Specification," document number X19A-A-002-xx. * When editing in 1354CFG with CRT enabled and panel disabled, select "Single Panel" from the "Edit Panel Setup" submenu. * When a CRT is enabled, the CRT settings will override the panel settings. If a panel is also used, the CRT timing values will have to be changed to more closely match the panel's timing. * A CRT cannot show 15 or 16 bits-per-pixel. * Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached.
Program Messages
ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register SED1354FOA device. A 1354 device was not found at the configured addresses. Check the configuration address using the 1354CFG configuration program. ERROR: Did not detect SED1354. The HAL was unable to read the revision code register on the SED1354. Ensure that the SED1354 hardware is installed and that the hardware platform has been set up correctly.
SED1354 X19A-B-002-04
1354SHOW Demonstration Program Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
1354SPLT Display Utility
Document Number: X19A-B-003-04
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-003-04
1354SPLT Display Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
1354SPLT
1354SPLT demonstrates SED1354 split screen capability by showing two different areas of display memory on the screen simultaneously. Screen 1 shows horizontal bars, and Screen 2 shows vertical bars. Screen 1 memory is located at the start of the display buffer. Screen 2 memory is located immediately after Screen 1 in the display buffer. On user input or elapsed time, the line compare register value is changed to adjust the amount of area displayed on either screen. The 1354SPLT display utility must be configured and/or compiled to work with your hardware platform. Consult documentation for the program 1354CFG.EXE which can be used to configure 1354SPLT. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection.
SED1354 Supported Evaluation Platforms
1354SPLT has been tested with the following SED1354 supported evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx.
Installation
PC platform: copy the file 1354SPLT.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 1354SPLT to the system.
1354SPLT Display Utility Issue Date: 98/10/29
SED1354 X19A-B-003-04
Page 4
Epson Research and Development Vancouver Design Center
Usage
PC platform: at the prompt, type 1354splt [/a]. Embedded platform: execute 1354splt and at the prompt, type the command line argument. Where: no argument /a enables manual split screen operation enables automatic split screen operation
The following keyboard commands are for navigation within the program. Manual mode: HOME END moves Screen 2 up moves Screen 2 down covers Screen 1 with Screen 2 displays only Screen 1
Automatic mode:
Z
changes the direction of split-screen movement
Both modes:
B ESC
changes the color depth (bits-per-pixel) exits 1354SPLT
1354SPLT Example
1. 2. 3. 4. Type "1354splt /a" to automatically move the split screen. Press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel. Repeat step 2 for the remaining bits-per-pixel colour depths: 1, 2, 4, 8, 15, and 16. Press to exit the program.
SED1354 X19A-B-003-04
1354SPLT Display Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 5
Comments
* The PC must not have more than 12M bytes of system memory when used with the SDU1354B0C board. * Follow simultaneous display guidelines for correct simultaneous display operation. * To determine if the CRT will operate correctly when using a dual panel, refer to the "Maximum Frame Rates" table in the SED1354 "Functional Hardware Specification," document number X19A-A-002-xx. * When editing in 1354CFG with CRT enabled and panel disabled, select "Single Panel" from the "Edit Panel Setup" submenu. * When a CRT is enabled, the CRT settings will override the panel settings. If a panel is also used, the CRT timing values will have to be changed to more closely match the panel's timing. * A CRT cannot show 15 or 16 bits-per-pixel. * Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached.
Program Messages
ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register SED1354FOA device. A 1354 device was not found at the configured addresses. Check the configuration address using the 1354CFG configuration program. ERROR: Did not detect SED1354. The HAL was unable to read the revision code register on the SED1354. Ensure that the SED1354 hardware is installed and that the hardware platform has been set up correctly.
1354SPLT Display Utility Issue Date: 98/10/29
SED1354 X19A-B-003-04
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-003-04
1354SPLT Display Utility Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
1354VIRT Display Utility
Document Number: X19A-B-004-04
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-004-04
1354VIRT Display Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
1354VIRT
1354VIRT shows the virtual display capability of the SED1354. A virtual display is where the image to be displayed is larger than the physical display device (CRT or LCD) and can be viewed by panning and scrolling. 1354VIRT allows the display device to be used as a "window" to view the entire image. The 1354VIRT display utility must be configured and/or compiled to work with your hardware platform. Consult documentation for the program 1354CFG.EXE which can be used to configure 1354VIRT. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection.
SED1354 Supported Evaluation Platforms
1354VIRT has been tested with the following SED1354 supported evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx.
Installation
PC platform: copy the file 1354VIRT.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 1354VIRT to the system.
1354VIRT Display Utility Issue Date: 98/10/29
SED1354 X19A-B-004-04
Page 4
Epson Research and Development Vancouver Design Center
Usage
PC platform: at the prompt, type 1354virt [/A] [/W=???]. Embedded platform: execute 1354virt and at the prompt, type the command line argument.
Where:
no argument /a /w=???
panning and scrolling is performed manually panning and scrolling is performed automatically for manual mode, specifies the width of the virtual display which must be a multiple of 8 and less than 1024 (the default width is 1024 pixels); the maximum height is based on the display memory and the width of the virtual display
The following keyboard commands are for navigation within the program. Manual mode: HOME END Automatic mode: Z scrolls up scrolls down pans to the left pans to the right moves the display screen so that the upper right of the virtual screen shows in the upper right of the display moves the display screen so that the lower left of the virtual screen shows in the lower left of the display changes the direction of screen
Both modes:
B ESC
changes the color depth (bits-per-pixel) exits 1354VIRT
1354VIRT Example
1. 2. 3. 4. Type "1354virt /a" to automatically pan and scroll. Press "b" to change the bits-per-pixel from 1 bit-per-pixel to 2 bits-per-pixel. Repeat steps 1 and 2 for the following bits-per-pixel values: 1, 2, 4, 8, 15, and 16. Press to exit the program.
SED1354 X19A-B-004-04
1354VIRT Display Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 5
Comments
* The maximum virtual display width is 1024 pixels, except in 15 and 16 bits-per-pixel mode where the maximum width is 1023 pixels. * The PC must not have more than 12M bytes of system memory when used with the SDU1354B0C board. * Follow simultaneous display guidelines for correct simultaneous display operation. * To determine if the CRT will operate correctly when using a dual panel, refer to the "Maximum Frame Rates" table in the SED1354 "Functional Hardware Specification," document number X19A-A-002-xx. * When editing in 1354CFG with CRT enabled and panel disabled, select "Single Panel" from the "Edit Panel Setup" submenu. * When a CRT is enabled, the CRT settings will override the panel settings. If a panel is also used, the CRT timing values will have to be changed to more closely match the panel's timing. * A CRT cannot show 15 or 16 bits-per-pixel. * Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached.
Program Messages
ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register SED1354FOA device. A 1354 device was not found at the configured addresses. Check the configuration address using the 1354CFG configuration program. ERROR: Did not detect SED1354. The HAL was unable to read the revision code register on the SED1354. Ensure that the SED1354 hardware is installed and that the hardware platform has been set up correctly.
1354VIRT Display Utility Issue Date: 98/10/29
SED1354 X19A-B-004-04
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-004-04
1354VIRT Display Utility Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
1354PLAY Diagnostic Utility
Document Number: X19A-B-005-04
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-005-04
1354PLAY Diagnostic Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
1354PLAY
1354PLAY allows the user to read/write to all SED1354 registers/look up tables and display memory. 1354PLAY is similar to the DOS DEBUG program; commands are received from the standard input device, and output is sent to the standard output device (console for Intel, terminal for embedded platforms). This utility requires the target platform to support standard IO (stdio). 1354PLAY commands can be entered interactively using a keyboard/monitor or they can be executed from a script file. Scripting is a powerful feature which allows command sequences to be used repeatedly without re-entry. The 1354PLAY display utility must be configured and/or compiled to work with your hardware platform. Consult documentation for the program 1354CFG.EXE which can be used to configure 1354PLAY. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection.
SED1354 Supported Evaluation Platforms
1354PLAY has been tested with the following SED1354 supported evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx.
Installation
PC platform: copy the file 1354PLAY.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 1354PLAY to the system.
1354PLAY Diagnostic Utility Issue Date: 98/10/29
SED1354 X19A-B-005-04
Page 4
Epson Research and Development Vancouver Design Center
Usage
PC platform: at the prompt, type 1354play [/?]. Embedded platform: execute 1354play and at the prompt, type the command line argument. Where: /? displays program revision information.
The following commands are valid within the 1354PLAY program.
X index [data]
- Reads/writes the registers. - Writes data to the register specified by the index when "data" is specified; otherwise the register is read.
XA D index [data1 data2 data3]
- Reads all registers. - Reads/writes DAC values. - Writes data to the DAC index when "data" is specified; otherwise the register is read. - Data consists of 3 bytes: 1 red, 1 green, 1 blue.
DA
L index [data1 data2 data3]
- Reads all DAC values. - Reads/writes Look-Up Table (LUT) values. - Writes data to the LUT index when "data" is specified; otherwise the LUT index is read. - Data consists of 3 bytes: 1 red, 1 green, 1 blue.
LA
F[W] addr1 addr2 data . . .
- Reads all LUT values. - Fills bytes or words from address 1 to address 2 with data. - Data can be multiple values (e.g. F 0 20 1 2 3 4 fills 0 to 0x20 with a repeating pattern of 1 2 3 4).
R[W] addr [count]
- Reads number of bytes or words from the address specified by "addr". If "count" is not specified, then 16 bytes/words are read. - Writes bytes or words of data to address specified by "addr". - Data can be multiple values (e.g. W 0 1 2 3 4 writes the byte values 1 2 3 4 starting at address 0).
W[W] addr data . . .
I M [bpp]
- Initializes the chip with user specified configuration. - Gets current mode information. - If "bpp" is specified then set that pixel depth.
SED1354 X19A-B-005-04
1354PLAY Diagnostic Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 5
P 1|0
- 1 = set/0 = reset hardware suspend (power mode). - This feature only works on the SDU1354B0B ISA evaluation board while operating in the x86 environment. - Do not use with the SDU1354B0C evaluation board.
H [lines]
- Halts after lines of display. This feature halts the display during long read operations to prevent data from scrolling off the display. - Set 0 to disable.
Q ?
- Quits this utility. - Displays Help information.
1354PLAY Example
1. 2. 3. 4. 5. 6. 7. 8. 9. Type "1354PLAY" to start the program. Type "?" for help. Type "i" to initialize the registers. Type "xa" to display the contents of the registers. Type "x 5" to read register 5. Type "x 3 10" to write 10 hex to register 3. Type "f 0 ffff aa" to fill the first FFFF hex bytes of display memory with AA hex. Type "f 0 1fffff aa" to fill 2M bytes of display memory. Type "r 0 ff" to read the first 100 hex bytes of display memory.
10. Type "q" to exit the program.
Scripting
1354PLAY can be driven by a script file. This is useful when: * there is no display output and a current register status is required * various registers must be quickly changed to view results. A script file is an ASCII text file with one 1354PLAY command per line. All scripts must end with a "q" (quit) command. On a PC platform, a typical script command line is: "1354PLAY < dumpregs.scr > results." This causes the file "dumpregs.scr" to be interpreted and the results to be sent to the file "results." Example: Create an ASCII text file that contains the commands i, xa, and q. ; This file initializes the SED1354 and reads the registers ; Note: after a semi-colon (;), all characters on a line are ignored i xa q
1354PLAY Diagnostic Utility Issue Date: 98/10/29
SED1354 X19A-B-005-04
Page 6
Epson Research and Development Vancouver Design Center
Comments
* All numeric values are considered to be hexadecimal unless identified otherwise. For example, 10 = 10h = 16 decimal; 10t = 10 decimal; 010b = 2 decimal. * Redirecting commands from a script file (PC platform) allows those commands to be executed as though they were typed. * The PC must not have more than 12M bytes of memory when used with the SDU1354B0C board. * Follow simultaneous display guidelines for correct simultaneous display operation. * To determine if the CRT will operate correctly when using a dual panel, refer to the "Maximum Frame Rates" table in the SED1354 "Functional Hardware Specification," document number X19A-A-002-xx. * When editing in 1354CFG with CRT enabled and panel disabled, select "Single Panel" from the "Edit Panel Setup" submenu. * When a CRT is enabled, the CRT settings will override the panel settings. If a panel is also used, the CRT timing values will have to be changed to more closely match the panel's timing. * A CRT cannot show 15 or 16 bits-per-pixel. * Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached.
Program Messages
ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register SED1354FOA device. A 1354 device was not found at the configured addresses. Check the configuration address using the 1354CFG configuration program.
SED1354 X19A-B-005-04
1354PLAY Diagnostic Utility Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
1354BMP Demonstration Program
Document Number: X19A-B-006-03
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-006-03
1354BMP Demonstration Program Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
1354BMP
1354BMP demonstrates SED1354 display capabilities by rendering bitmap images on the display. The 1354BMP display utility is designed to operate in a personal computer (PC) DOS environment and must be configured to work with your display hardware. Consult documentation for the program 1354CFG.EXE which can be used to configure 1354BMP. 1354BMP is not supported on non-PC platforms.
Installation
Copy the file 1354BMP.EXE to a directory that is in the DOS path on your hard drive.
Usage
At the prompt, type 1354bmp bmp file [/a] [/lcd] [/crt] [/?].
Where:
bmp file /a /lcd /crt /?
displays the bmp format file automatically exits after 5 seconds displays the image on a LCD displays the image on a CRT displays the Help screen
Comments
* 1354BMP only currently decodes Windows BMP format images. * The PC must not have more than 12M bytes of memory when used with the SDU1354B0C board. * Follow simultaneous display guidelines for correct simultaneous display operation. * To determine if the CRT will operate correctly when using a dual panel, refer to the "Maximum Frame Rates" table in the SED1354 "Functional Hardware Specification," document number X19A-A-002-xx. * When editing in 1354CFG with CRT enabled and panel disabled, select "Single Panel" from the "Edit Panel Setup" submenu. * When a CRT is enabled, the CRT settings will override the panel settings. If a panel is also used, the CRT timing values will have to be changed to more closely match the panel's timing. * A CRT cannot show 15 or 16 bits-per-pixel. * Do not attach a panel with a 16-bit interface to the SED1354 when a CRT is also attached.
1354BMP Demonstration Program Issue Date: 98/10/29
SED1354 X19A-B-006-03
Page 4
Epson Research and Development Vancouver Design Center
Program Messages
ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register SED1354FOA device. A 1354 device was not found at the configured addresses. Check the configuration address using the 1354CFG configuration program. ERROR: Did not detect SED1354. The HAL was unable to read the revision code register on the SED1354. Ensure that the SED1354 hardware is installed and that the hardware platform has been set up correctly.
SED1354 X19A-B-006-03
1354BMP Demonstration Program Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
1354PWR Software Suspend Power Sequencing Utility
Document Number: X19A-B-007-03
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-007-03
1354PWR Software Suspend Power Sequencing Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
1354PWR
The 1354PWR Software Suspend Power Sequencing Utility enables or disables the SED1354 software suspend mode and LCD. Refer to the section titled "LCD Power Sequencing and Power Save Modes" in the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx. Also, refer to the SED1354 "Functional Hardware Specification," document number X19A-A-002-xx for further information. The 1354PWR display utility must be configured and/or compiled to work with your hardware platform. Consult documentation for the program 1354CFG.EXE which can be used to configure 1354PWR. This software is designed to work in both embedded and personal computer (PC) environments. For the embedded environment, it is assumed that the system has a means of downloading software from the PC to the target platform. Typically this is done by serial communications, where the PC uses a terminal program to send control commands and information to the target processor. Alternatively, the PC can program an EPROM, which is then placed in the target platform. Some target platforms can also communicate with the PC via a parallel port connection, or an Ethernet connection.
SED1354 Supported Evaluation Platforms
1354PWR has been tested with the following SED1354 supported evaluation platforms: * PC system with an Intel 80x86 processor. * M68332BCC (Business Card Computer) board, revision B, with a Motorola MC68332 processor. * M68EC000IDP (Integrated Development Platform) board, revision 3.0, with a Motorola M68EC000 processor. * SH3-LCEVB board, revision B, with an Hitachi SH-3 HD6417780 processor. If the platform you are using is different from the above, please see the SED1354 "Programming Notes and Examples" manual, document number X19A-G-002-xx.
Installation
PC platform: copy the file 1354PWR.EXE to a directory that is in the DOS path on your hard drive. Embedded platform: download the program 1354PWR to the system.
1354PWR Software Suspend Power Sequencing Utility Issue Date: 98/10/29
SED1354 X19A-B-007-03
Page 4
Epson Research and Development Vancouver Design Center
Usage
PC platform: at the prompt, type 1354pwr [/software /lcd] [/enable /disable] [/i] [/?]. Embedded platform: execute 1354pwr and at the prompt, type the command line argument.
Where:
/software /lcd /enable /disable /i /?
selects software suspend selects the LCD activates software suspend or the LCD deactivates software suspend or the LCD initializes registers displays this usage message
Examples
To enable software suspend mode, use the following arguments: /software /enable To disable software suspend mode, use the following arguments: /software /disable To enable the LCD, use the following arguments: /lcd /enable To disable the LCD, use the following arguments: /lcd /disable
Comments
* The /i argument is to be used when the registers have not been previously initialized. * The PC must not have more than 8M bytes of memory when used with the SDU1354B0B board. * Follow simultaneous display guidelines for correct simultaneous display operation. * Do not use a dual panel with a CRT. Select "Panel Single" whenever using a CRT, even if a panel is not attached. Also, the panel section of 1354CFG must be programmed to "Single Panel." * When a CRT is enabled, the settings for the CRT will override the panel settings. If a panel is also used, the CRT timing values will have to be changed to more closely match the panel's timing. * A CRT cannot show 15 or 16 bits-per-pixel. * Do not attach a 16-bit panel when using the CRT.
SED1354 X19A-B-007-03
1354PWR Software Suspend Power Sequencing Utility Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 5
Program Messages
ERROR: Unknown command line argument. An invalid command line argument was entered. Enter a valid command line argument. ERROR: Already selected SOFTWARE. Command line argument /software was selected more than once. Select /software only once. ERROR: Already selected HARDWARE. Command line argument /hardware was selected more than once. Select /hardware only once. ERROR: Already selected ENABLE. Command line argument /enable was selected more than once. Select /enable only once. ERROR: Already selected DISABLE. Command line argument /disable was selected more than once. Select /disable only once. ERROR: Select /software or /hardware. Neither command line argument /software or /hardware was selected. Select /software or
/hardware.
ERROR: Select /enable or /disable. Neither command line argument /enable or /disable was selected. Select /enable or /disable. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL can only manage 10 devices simultaneously. ERROR: Could not register SED1354FOA device. A 1354 device was not found at the configured addresses. Check the configuration address using the 1354CFG configuration program. ERROR: Did not detect SED1354. The HAL was unable to read the revision code register on the SED1354. Ensure that the SED1354 hardware is installed and that the hardware platform has been set up correctly.
1354PWR Software Suspend Power Sequencing Utility Issue Date: 98/10/29
SED1354 X19A-B-007-03
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-B-007-03
1354PWR Software Suspend Power Sequencing Utility Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
Windows(R) CE Display Drivers
Document Number: X19A-E-001-03
Copyright (c) 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-E-001-03
Windows(R) CE Display Drivers Issue Date: 98/12/21
Epson Research and Development Vancouver Design Center
Page 3
WINDOWS(R) CE DISPLAY DRIVERS
The Windows CE display drivers are designed to support the SED1354 Color Graphics LCD/CRT Controller running under the Microsoft Windows CE operating system. Drivers are available for 4, 8 and 16 bit-per-pixel modes. For updated source code, visit Epson R&D on the World Wide Web at www.erd.epson.com, or contact your Seiko Epson or Epson Electronics America sales representative.
Program Requirements
Video Controller Display Type Windows Version : SED1354 : LCD or CRT : CE Version 2.0
Example Driver Builds
Build for the Hitachi D9000 and ETMA ODO Evaluation Systems To build a Windows CE v2.0 display driver for the Hitachi D9000 or ETMA ODO platform follow the instructions below. The instructions assume the SDU1354-D9000 evaluation board is plugged into slots 6 and 7 on the D9000/ODO platform, and the SEIKO EPSON common interface FPGA (ODO.RBF) is used to interface with the SED1354. Check to ensure that the DIP switches on the SDU1354-D9000 board are set as follows:
DIP Switch 1 ON 2 ON 3 OFF 4 OFF
1. 2. 3. 4.
Install Microsoft Windows NT v4.0. Install Microsoft Visual C/C++ v5.0. Install the Microsoft Windows CE Embedded Toolkit (ETK) by running SETUP.EXE from the ETK compact disc #1. Create a new project by following the procedure documented in "Creating a New Project Directory" from the Windows CE ETK v2.0. Alternately, use the current "DEMO7" project included with the ETK v2.0. Follow the steps below to create a "SH3 DEMO7" shortcut on the Windows NT v4.0 desktop which uses the current "DEMO7" project: a. Right click on the "Start" menu on the taskbar. b. Click on the item "Open All Users" and the "Start Menu" window will come up. c. Click on the icon "Programs". d. Click on the icon "Windows CE Embedded Development Kit". e. Drag the icon "SH3 DEMO1" onto the desktop using the right mouse button. f. Click on "Copy Here".
Windows(R) CE Display Drivers Issue Date: 98/12/21
SED1354 X19A-E-001-03
Page 4
Epson Research and Development Vancouver Design Center
g. Rename the icon "SH3 DEMO1" on the desktop to "SH3 DEMO7" by right clicking on the icon and choosing "rename". h. Right click on the icon "SH3 DEMO7" and click on "Properties" to bring up the "SH3 DEMO7 Properties" window. i. Replace the string "DEMO1" under the entry "Target" with "DEMO7". j. Click on "OK" to finish. 5. 6. 7. 8. Create a sub-directory named SED1354 under \wince\platform\odo\drivers\display. Copy the source code to the SED1354 subdirectory. Add an entry for the SED1354 in the file \wince\platform\odo\drivers\display\dirs. Modify the file PLATFORM.BIB (using any text editor such as NOTEPAD) to set the default display driver to the file SED1354.DLL. SED1354.DLL will be created during the build. Note that PLATFORM.BIB is located in X:\wince\platform\odo\files (where X: is the drive letter). You may replace the following lines in PLATFORM.BIB:
IF ODO_NODISPLAY ! IF ODO_DISPLAY_CITIZEN_8BPP ddi.dll ENDIF IF ODO_DISPLAY_CITIZEN_2BPP ddi.dll ENDIF IF ODO_DISPLAY_CITIZEN_8BPP ! IF ODO_DISPLAY_CITIZEN_2BPP ! ddi.dll ENDIF ENDIF ENDIF $(_FLATRELEASEDIR)\odo2bpp.dll NK SH $(_FLATRELEASEDIR)\citizen.dll NK SH $(_FLATRELEASEDIR)\citizen.dll NK SH
with this line:
ddi.dll $(_FLATRELEASEDIR)\SED1354.dll NK SH
9.
Edit the file MODE.H (located in X:\wince\platform\odo\drivers\display\SED1354) to set the desired screen resolution, color depth (bpp) and panel type. The sample code defaults to a 640x480 color dual passive 16-bit LCD panel. To support one of the other listed panels, change the #define statement.
SED1354 X19A-E-001-03
Windows(R) CE Display Drivers Issue Date: 98/12/21
Epson Research and Development Vancouver Design Center
Page 5
10. Edit the file PLATFORM.REG to set the same screen resolution and color depth (bpp) as in MODE.H. PLATFORM.REG is located in X:\wince\platform\odo\files. The display driver section of PLATFORM.REG should be:
; Default for EPSON Display Driver ; 640x480 at 8bits/pixel ; Useful Hex Values (for the lazy developer types) ; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0 [HKEY_LOCAL_MACHINE\Drivers\Display\SED1354] "CxScreen"=dword:280 "CyScreen"=dword:1E0 "Bpp"=dword:8
11. Generate the proper building environment by double-clicking on the sample project icon (i.e., SH3 DEMO7). 12. Type BLDDEMO at the DOS prompt of the SH3 DEMO7 window to generate a Windows CE image file (NK.BIN). Build For CEPC (X86) To build a Windows CE v2.0 display driver for the CEPC (X86) platform using a SDU1354B0C evaluation board, follow the instructions below: 1. 2. 3. 4. Install Microsoft Windows NT v4.0. Install Microsoft Visual C/C++ v5.0. Install the Microsoft Windows CE Embedded Toolkit (ETK) by running SETUP.EXE from the ETK compact disc #1. Create a new project by following the procedure documented in "Creating a New Project Directory" from the Windows CE ETK v2.0. Alternately, use the current "DEMO7" project included with the ETK v2.0. Follow the steps below to create a "X86 DEMO7" shortcut on the Windows NT v4.0 desktop which uses the current "DEMO7" project: a. Right click on the "Start" menu on the taskbar. b. Click on the item "Open All Users" and the "Start Menu" window will come up. c. Click on the icon "Programs". d. Click on the icon "Windows CE Embedded Development Kit". e. Drag the icon "X86 DEMO1" onto the desktop using the right mouse button. f. Click on "Copy Here". g. Rename the icon "X86 DEMO1" on the desktop to "X86 DEMO7" by right clicking on the icon and choosing "rename". h. Right click on the icon "X86 DEMO7" and click on "Properties" to bring up the "X86 DEMO7 Properties" window. i. Replace the string "DEMO1" under the entry "Target" with "DEMO7". j. Click on "OK" to finish.
Windows(R) CE Display Drivers Issue Date: 98/12/21
SED1354 X19A-E-001-03
Page 6
Epson Research and Development Vancouver Design Center
5. 6. 7.
Create a sub-directory named SED1354 under \wince\platform\cepc\drivers\display. Copy the source code to the SED1354 subdirectory. Add an entry for the SED1354 in the file \wince\platform\cepc\drivers\display\dirs.
SED1354 X19A-E-001-03
Windows(R) CE Display Drivers Issue Date: 98/12/21
Epson Research and Development Vancouver Design Center
Page 7
8.
Modify the file CONFIG.BIB (using any text editor such as NOTEPAD) to set the system RAM size and the SED1354 IO port and display buffer address mapping. Note that CONFIG.BIB is located in X:\wince\platform\cepc\files (where X: is the drive letter). Since the SDU1354B0C maps the IO port to 0xC00000 and memory to 0xE00000, the CEPC machine should use the CMOS setup to create a 4M byte hole from address 0xC00000 to 0xFFFFFF. The following lines should be in CONFIG.BIB: NK 80200000 00500000 RAMIMGE RAM 80700000 00500000 RAM
Note SED1354.H should include the following lines: #define PhysicalVmemSize 0x00200000L #define PhysicalPortAddr 0x00C00000L #define PhysicalVmemAddr 0x00E00000L 9. Edit the file PLATFORM.BIB (located in X:\wince\platform\cepc\files) to set the default display driver to the file SED1354.DLL. SED1354.DLL will be created during the build in step 13. You may replace the following lines in PLATFORM.BIB:
IF CEPC_DDI_VGA2BPP ddi.dll ENDIF IF CEPC_DDI_VGA8BPP ddi.dll ENDIF IF CEPC_DDI_VGA2BPP ! IF CEPC_DDI_VGA8BPP ! ddi.dll ENDIF ENDIF $(_FLATRELEASEDIR)\ddi_s364.dll NK SH $(_FLATRELEASEDIR)\ddi_vga8.dll NK SH $(_FLATRELEASEDIR)\ddi_vga2.dll NK SH
with this line:
ddi.dll $(_FLATRELEASEDIR)\SED1354.dll NK SH
10. Edit the file MODE.H (located in X:\wince\platform\odo\drivers\display\SED1354) to set the desired screen resolution, color depth (bpp) and panel type. The sample code defaults to 640x480 color dual passive 16-bit LCD panel. To support one of the other listed panels, change the #define statement. 11. Edit the file PLATFORM.REG to set the same screen resolution and color depth (bpp) as in MODE.H. PLATFORM.REG is located in X:\wince\platform\cepc\files. The display driver section of PLATFORM.REG should be:
; Default for EPSON Display Driver ; 640x480 at 8bits/pixel ; Useful Hex Values (for the lazy developer types)
Windows(R) CE Display Drivers Issue Date: 98/12/21
SED1354 X19A-E-001-03
Page 8
Epson Research and Development Vancouver Design Center
; 1024=0x400, 768=0x300 640=0x280 480=0x1E0 320=140 240=0xF0 [HKEY_LOCAL_MACHINE\Drivers\Display\SED1354] "CxScreen"=dword:280 "CyScreen"=dword:1E0 "Bpp"=dword:8
12. Generate the proper building environment by double-clicking on the sample project icon (i.e. X86 DEMO7). 13. Type BLDDEMO at the DOS prompt of the X86 DEMO7 window to generate a Windows CE image file (NK.BIN).
SED1354 X19A-E-001-03
Windows(R) CE Display Drivers Issue Date: 98/12/21
Epson Research and Development Vancouver Design Center
Page 9
Example Installation
Installation for Hitachi D9000 and ETMA ODO Follow the procedures from your Hitachi D9000 manual and download the following to the D9000 platform: 1. 2. Download SEIKO EPSON's common interface FPGA code (ODO.RBF) to the EEPROM of the D9000 system. Download the Windows CE binary ROM image (NK.BIN) to the FLASH memory of the D9000 system.
Installation for CEPC Environment Windows CE v2.0 can be loaded on a PC using a floppy drive or a hard drive. The two methods are described below: 1. To load CEPC from a floppy drive: a. b. c. Create a DOS bootable floppy disk. Edit CONFIG.SYS on the floppy disk to contain the following line only. device=a:\himem.sys Edit AUTOEXEC.BAT on the floppy disk to contain the following lines. mode com1:9600,n,8,1 loadcepc /B:9600 /C:1 /D:2 c:\wince\release\nk.bin Copy LOADCEPC.EXE from c:\wince\public\common\oak\bin to the bootable floppy disk. Confirm that NK.BIN is located in c:\wince\release. Reboot the system from the bootable floppy disk.
d. e. f. 2.
To load CEPC from a hard drive: a. b. c. Copy LOADCEPC.EXE to the root directory of the hard drive. Edit CONFIG.SYS on the hard drive to contain the following line only. device=c:\himem.sys Edit AUTOEXEC.BAT on the hard drive to contain the following lines. mode com1:9600,n,8,1 loadcepc /B:9600 /C:1 /D:2 c:\wince\release\nk.bin Confirm that NK.BIN is located in c:\wince\release. Reboot the system from the hard drive.
d. e.
Windows(R) CE Display Drivers Issue Date: 98/12/21
SED1354 X19A-E-001-03
Page 10
Epson Research and Development Vancouver Design Center
Comments
* Some of the D9000 systems may not be able to provide enough current for your LCD panel to operate properly. If this is the case, an external power supply should be connected to the panel. * The Seiko Epson Common Interface FPGA code assumes the display buffer starts at 0x12200000 and IO starts at 0x12000000. If the display buffer or IO location is modified, the corresponding entries in the file SED1354.H have to be changed. SED1354.H is located in X:\wince\platform\odo\drivers\display\SED1354 (where X: is the drive letter). * The External RAMDAC is decoded at the even addresses on a little-endian system. The RAMDAC registers are mapped as follows: * RAMDAC Pixel Read Mask Register is REG[28h] * RAMDAC Read Mode Address Register is REG[2Ah] * RAMDAC Write Mode Address Register is REG[2Ch] * RAMDAC Palette Data Register is REG[2Eh] * The driver is CPU independent but will require another ODO.RBF file to support other CPUs when running on the Hitachi D9000 or ETMA ODO platform. Please check with Seiko Epson for the latest supported CPU ODO files. * As the time of this printing, the drivers have been tested on the SH-3 and x86 CPUs and have only been run with v2.0 of the ETK. We are constantly updating the drivers so please check our website at www.erd.epson.com, or contact your Seiko Epson or Epson Electronics America sales representative.
SED1354 X19A-E-001-03
Windows(R) CE Display Drivers Issue Date: 98/12/21
SED1354 Color Graphics LCD/CRT Controller
SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Document Number: X19A-G-004-05
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 3 4 5 6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LCD / RAMDAC Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 CPU / BUS Interface Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 ISA Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Non-ISA Bus Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DRAM Support Decode Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . . . 15 . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock Input Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Monochrome LCD Panel Support Color TFT LCD Panel Support Color Passive LCD Panel Support . . . . . . . . . . . . . . . . . . . . . . . . . 15 External CMOS RAMDAC Support
6.10 Power Save Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.11 Core VDD Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.12 IO VDD Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.13 Adjustable LCD Panel Negative Power Supply . . . . . . . . . . . . . . . . . . . .16 6.14 Adjustable LCD Panel Positive Power Supply . . . . . . . . . . . . . . . . . . . . 16 6.15 CPU/Bus Interface Header Strips . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.16 Schematic Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 8 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 2-1: Table 2-2: Table 2-3: Table 3-1: Table 4-1: Table 4-2: Table 5-1: Configuration DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 LCD Signal Connector (J6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 CPU/BUS Connector (H1) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CPU/BUS Connector (H2) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: SED1354B0C Schematic Diagram (1 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SED1354B0C Schematic Diagram (2 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SED1354B0C Schematic Diagram (3 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SED1354B0C Schematic Diagram (4 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SED1354B0C Schematic Diagram (5 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SED1354B0C Schematic Diagram (6 of 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This manual describes the setup and operation of the SDU1354B0C Rev. 1.0 Evaluation Board when used with the SED1354 Color Graphics LCD/CRT Controller in the ISA bus environment. For more information regarding the SED1354, refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx.
1.1 Features
* 128 pin QFP15 package. * SMT technology for all appropriate devices. * 4/8-bit monochrome passive LCD panels support. * 4/8/16-bit color passive LCD panels support. * 9/12/18-bit LCD TFT panels support. * External RAMDAC support. * 16-bit ISA bus support. * Oscillator support for CLKI (up to 40.0MHz). * 5.0V 1M x 16 EDO-DRAM. * Support for software power save modes. * 3.3V Core VDD power supply. * Selectable 3.3V or 5.0V IO VDD power supply (via jumper JP2). * On-board adjustable LCD BIAS negative power supply (-14V to -24V). * On-board adjustable LCD BIAS positive power supply (+23V to +40V). * CPU/Bus interface header strips for non-ISA bus support.
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 8
Epson Research and Development Vancouver Design Center
2 Installation and Configuration
The SED1354 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. SED1354 configuration inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one five-position DIP switch is provided for this purpose. All remaining configuration inputs are hard-wired. See the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for more information. When using the SDU1354B0C with the ISA bus, the following are the recommended settings. Table 2-1: Configuration DIP Switch Settings
Switch Signal SW1-1 MD1 SW1-2 MD2 SW1-3 MD3 SW1-4 MD4 SW1-5 MD5 Little Endian Wait# signal is active high Big Endian Wait# signal is active low See "Host Bus Selection" table below See "Host Bus Selection" table below Closed Open
The polarity of the Configuration DIP Switches is closed = 1 or high; open = 0 or low. = required settings for ISA bus support.
Table 2-2: Host Bus Selection
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Option 1 2 3 4 5 Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. ISA bus) Reserved
Closed = 1 or high; open = 0 or low. = required settings for ISA bus support.
Table 2-3: Jumper Settings
Description JP1 JP2 JP3
.
1-2 Pulled-up to IO VDD for ISA bus 5.0V IO VDD Support for all panels which require MOD/DRDY signal
2-3 NC, signal may be needed for 68K bus and other bus support 3.3V IO VDD Support for 8-bit panels which require 2 shift clocks
BS# signal pin 6 selection 3.3V/5.0V IO VDD selection DRDY signal selection
= default settings for ISA bus and LCD panel support.
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 9
3 LCD / RAMDAC Interface Pin Mapping
Table 3-1: LCD Signal Connector (J6)
Color TFT SED1354 Pin Names FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPSHIFT DRDY FPLINE FPFRAME DACP0 DACRD# DACWR# DACRS1 DACRS0 HRTC VRTC BLANK# DACCLK GND N/C VLCD VCC +12V VDDH DRDY LCDPWR 2-26 (Even Pins) 28 30 32 34 36 38 40 DRDY LCD PWR# DRDY LCD PWR# DRDY LCD PWR# +5V +12V +5V +12V +5V +12V +5V +12V VDDH MOD LCD PWR# +5V +12V VDDH FPSHIFT2 LCD PWR# VLCD +5V +12V VDDH MOD LCD PWR# MOD LCD PWR# MOD LCD PWR# LCD PWR# VLCD +5V +12V +5V +12V GND GND GND GND GND GND GND GND Connector Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 FPLINE FPLINE FPLINE FPFRAME FPLINE FPFRAME FPFRAME FPFRAME FPSHIFT FPSHIFT B0 G0 9-bit R2 R1 R0 G2 G1 G0 B2 B1 B0 12-bit R3 R2 R1 G3 G2 G1 B3 B2 B1 R0 18-bit R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 G2 G1 G0 B2 B1 FPSHIFT FPSHIFT FPSHIFT FPSHIFT2 FPLINE FPFRAME FPLINE FPFRAME FPLINE FPFRAME FPLINE FPFRAME DACP0 DACRD# DACWR# DACRS1 DACRS0 HRTC VRTC BLANK# PCLK GND UD0 UD1 UD2 UD3 4-bit Color Passive 8-bit LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 16-bit LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 FPSHIFT FPSHIFT FPSHIFT DACP7 DACP6 DACP5 DACP4 DACP3 DACP2 DACP1 UD0 UD1 UD2 UD3 Mono Passive 4-bit 8-bit LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 External RAMDAC (CRT)
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 10
Epson Research and Development Vancouver Design Center
4 CPU / BUS Interface Connector Pinouts
Table 4-1: CPU/BUS Connector (H1) Pinout
Connector Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Comments Connected to DB0 of the SED1354 Connected to DB1 of the SED1354 Connected to DB2 of the SED1354 Connected to DB3 of the SED1354 Ground Ground Connected to DB4 of the SED1354 Connected to DB5 of the SED1354 Connected to DB6 of the SED1354 Connected to DB7 of the SED1354 Ground Ground Connected to DB8 of the SED1354 Connected to DB9 of the SED1354 Connected to DB10 of the SED1354 Connected to DB11 of the SED1354 Ground Ground Connected to DB12 of the SED1354 Connected to DB13 of the SED1354 Connected to DB14 of the SED1354 Connected to DB15 of the SED1354 Connected to RESET# of the SED1354 Ground Ground Ground 12 volt supply 12 volt supply Connected to WE0# of the SED1354 Connected to WAIT# of the SED1354 Connected to CS# of the SED1354 Connected to MR# of the SED1354 Connected to WE#1 of the SED1354 Not connected
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 11
Table 4-2: CPU/BUS Connector (H2) Pinout
Connector Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Comments Connected to AB0 of the SED1354 Connected to AB1 of the SED1354 Connected to AB2 of the SED1354 Connected to AB3 of the SED1354 Connected to AB4 of the SED1354 Connected to AB5 of the SED1354 Connected to AB6 of the SED1354 Connected to AB7 of the SED1354 Ground Ground Connected to AB8 of the SED1354 Connected to AB9 of the SED1354 Connected to AB10 of the SED1354 Connected to AB11 of the SED1354 Connected to AB12 of the SED1354 Connected to AB13 of the SED1354 Ground Ground Connected to AB14 of the SED1354 Connected to AB14 of the SED1354 Connected to AB16 of the SED1354 Connected to AB17 of the SED1354 Connected to AB18 of the SED1354 Connected to AB19 of the SED1354 Ground Ground 5 volt supply 5 volt supply Connected to RD/WR# of the SED1354 Connected to BS# of the SED1354 Connected to BUSCLK of the SED1354 Connected to RD# of the SED1354 Connected to AB20 of the SED1354 Not connected
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 12
Epson Research and Development Vancouver Design Center
5 Host Bus Interface Pin Mapping
Table 5-1: Host Bus Interface Pin Mapping SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# SH-3 A[20:1] A0 D[15:0] WE1# External Decode CSn# CKIO BS# RD/WR# RD# WE0# WAIT# RESET# MC68K Bus 1 A[20:1] LDS# D[15:0] UDS# External Decode External Decode CLK AS# R/W# Connect to IO VDD Connect to IO VDD DTACK# RESET# MC68K Bus 2 A[20:1] A0 D[31:16] DS# External Decode External Decode CLK AS# R/W# SIZ1 SIZ0 DSACK1# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 13
6 Technical Description
6.1 ISA Bus Support
The SDU1354B0C directly supports the 16-bit ISA bus environment. All the configuration options [MD15:0] are either hard-wired or selectable through the five-position DIP Switch S1. Refer to Table 2-1 "Configuration DIP Switch Settings," on page 8 for details. Note 1. The 8-bit ISA bus is not supported by the SDU1354B0C board design. 2. The SED1354 is a memory-mapped device with 2M bytes of linear addressed display buffer memory as well as a separate 37 byte register space. On the SDU1354B0C, the SED1354 registers have been mapped to a start-address of C00000h and the 2M byte display buffer has been mapped to a start-address of E00000h. 3. When using this board in a PC environment, system memory must be limited to 12M bytes as more than this will conflict with the SED1354 display buffer/register addresses. Note Due to backwards compatibility with the SDU1354B0B Evaluation Board, which supports both an 8 and a 16-bit CPU interface, third party software must perform a write to address D00000h to enable a 16-bit ISA environment. This must be done prior to initializing the SED1354. Failure to do so will result in the SED1354 being configured as a 16-bit device (default, power-up), with the ISA Bus interface (supported through the PAL (U4)) configured for an 8-bit interface. The Epson supplied software performs this function automatically.
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 14
Epson Research and Development Vancouver Design Center
6.2 Non-ISA Bus Support
This evaluation board is specifically designed to support the standard 16-bit ISA bus, however, the SED1354 directly supports many other host bus interfaces. Header strips (H1 and H2) have been provided and contain all the necessary IO pins to interface to these buses. See Section 4, "CPU / BUS Interface Connector Pinouts" on page 10; Table 2-1 "Configuration DIP Switch Settings," on page 8; and Table 2-3 "Jumper Settings," on page 8 for details. When using the header strips to provide the bus interface observe the following: * All IO signals on the ISA bus card edge must be isolated from the ISA bus (do not plug the card into a computer). Voltage lines are provided on the header strips. * U3, a TIBPAL22V10 PAL, is currently used to provide the SED1354 CS# (pin 4), M/R# (pin 5) and other decode logic signals for ISA bus use. This functionality must now be provided externally; remove the PAL from its socket to eliminate conflicts resulting from two different outputs driving the same input. Refer to Table 5-1: "Host Bus Interface Pin Mapping," on page 12 for connection details. Note When using a 3.3V CPU Interface, JP2 must be used to configure the SED1354 IO VDD to 3.3V. In this configuration all SED1354 IO pins are configured for 3.3V output (e.g. LCD interface, DRAM interface, RAMDAC interface, etc.). Although the DRAM and RAMDAC devices are 5.0V parts, they only require a TTL VIH of 2.4V, therefore they will operate correctly with the CMOS level output drive of the SED1354.
6.3 DRAM Support
The SED1354 supports 256K x 16 as well as 1M x 16 DRAM (FPM and EDO) in symmetrical and asymmetrical formats. The SDU1354B0C board supports 5.0V 1M x 16 EDO-DRAM (42-pin SOJ package) in symmetrical format, providing a 2M byte display buffer.
6.4 Decode Logic
This board design utilizes the Generic MPU Interface of the SDU1354 (see the SED1354 Hardware Functional Specification, document number X19A-A-002-xx). All required decode logic between the ISA bus and the SED1354 is provided through a TIBPAL22V10 PAL (U3, socketed).
6.5 Clock Input Support
The input clock frequency can be up to 40.0MHz for the SED1354. A 40.0MHz oscillator (U4, socketed) is provided as the clock (CLKI) source.
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 15
6.6 Monochrome LCD Panel Support
The SED1354 supports 4 and 8-bit dual and single, monochrome passive LCD panels. All necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals are alternated with grounds on the cable to reduce cross-talk and noise-related problems. Refer to Table 3-1 "LCD Signal Connector (J6)," on page 9 for connection information.
6.7 Color Passive LCD Panel Support
The SED1354 directly supports 4/8/16-bit dual and single, color passive LCD panels. All the necessary signals are provided on the 40-pin ribbon cable header J6. The interface signals are alternated with grounds on the cable to reduce cross-talk and noise-related problems. The SED1354 cannot support 12 or 18-bit TFT panels when CRT is enabled. FPDAT [15:8] is used for RAMDAC data and is not available for LCD. Refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for details. Refer to Table 3-1 "LCD Signal Connector (J6)," on page 9 for connection information.
6.8 Color TFT LCD Panel Support
The SED1354 supports 9/12/18-bit active matrix color TFT panels. All the necessary signals can also be found on the 40-pin LCD connector J6. The interface signals are alternated with grounds on the cable to reduce cross-talk and noise-related problems. When supporting an 18-bit TFT panel, the SED1354 can display 64K of a possible 262K colors. A maximum 16 of the possible 18-bits of LCD data is available from the SED1354. Refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for details. The SED1354 cannot support 12 or 18-bit TFT panels when CRT is enabled. FPDAT [15:8] is used for RAMDAC data and is not available for LCD. Refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for details. Refer to Table 3-1 "LCD Signal Connector (J6)," on page 9 for connection information.
6.9 External CMOS RAMDAC Support
This evaluation board design provides CRT support with the addition of an external RAMDAC (BrookTree BT481A or equivalent). The presence of an external RAMDAC/CRT can be determined by software once the SED1354 is properly initialized after power-up. The BT481A RAMDAC is provided on the board to fully test all of the CRT display modes available. Refer to the section "Display Support" of the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for details. The overlay function and sprite/hardware cursor display features are not supported.
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 16
Epson Research and Development Vancouver Design Center
6.10 Power Save Modes
The SED1354F0A supports one hardware and one software suspend Power Save Mode. The hardware suspend mode is not supported by the SDU1354B0C. The software suspend mode is controlled by the utility 1354PWR Software Suspend Power Sequencing.
6.11 Core VDD Power Supply
An independent fixed 3.3V power supply for Core VDD is provided. A National LP2960AIN-3.3 voltage regulator is used for the power supply and is capable of supplying 500mA @ 3.3V.
6.12 IO VDD Power Supply
The IO VDD voltage is selectable between 3.3V and 5.0V through jumper JP2. For the 5.0V host bus interface, select IO VDD at 5.0V, and for the 3.3V host bus interface, select IO VDD at 3.3V. Refer to Table 2-3 "Jumper Settings," on page 8.
6.13 Adjustable LCD Panel Negative Power Supply
Most monochrome passive LCD panels require a negative power supply to provide between -18V and -23V (Iout=45mA). For ease of implementation, such a power supply has been provided as an integral part of this design. The signal VLCD can be adjusted by R37 to supply an output voltage from -14V to -23V and is enabled/disabled by the SED1354 control signal LCDPWR. Determine the panel's specific power requirements and set the potentiometer accordingly before connecting the panel.
6.14 Adjustable LCD Panel Positive Power Supply
Most passive LCD passive color panels and most single monochrome 640x480 passive LCD panels require a positive power supply to supply between +23V and +40V (Iout=45mA). For ease of implementation, such a power supply has been provided as an integral part of this design. The signal VDDH can be adjusted by R31 to provide an output voltage from +23V to +40V and is enabled/disabled by the SED1354 control signal LCDPWR. Determine the panel's specific power requirements and set the potentiometer accordingly before connecting the panel.
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 17
6.15 CPU/Bus Interface Header Strips
All of the CPU/Bus interface pins of the SED1354 are connected to the header strips H1 and H2 for easy interface to a CPU/Bus other than the ISA bus. Refer to Table 4-1 "CPU/BUS Connector (H1) Pinout," on page 10 and Table 4-2 "CPU/BUS Connector (H2) Pinout," on page 11 for specific settings. Note These headers only provide the CPU/Bus interface signals from the SED1354. When another host bus interface is selected through [MD3:1] configuration, appropriate external decode logic MUST be used to access the SED1354. See the section "Host Bus Interface Pin Mapping" of the SED1354 Hardware Functional Specification, document number X19A-A-002-xx.
6.16 Schematic Notes
The following schematics are for reference only and may not reflect actual implementation. Please request updated information before starting any hardware design.
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 18
Epson Research and Development Vancouver Design Center
7 Parts List
Item # Qty/board 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 4 16 3 3 3 1 1 6 3 2 1 1 8 1 1 1 9 1 3 6 3 8 3 1 1 1 1 1 1 Designation C13, C14, C19, C28 10uF Part Value Description 10uF/25V Tantalum D-Size 0.01uF, 1206 package 0.1uF, 1206 package Electrolytic/Radial (LXF63VB10RM5X11LL) LXF35VB56RM6X11LL 33uF/10V Tantalum D-Size TO-92 PTH Zener Diode 0.1" spc. 3 pin TO-92 package Signal Diode/PTH PTH; include 2 pin jumper (shunt) 0.1" 2 x 17 Male Header Assman A-HDF 15 A KG/T or equivalent Shrouded Header 40 pin Dual-row, center-key PTH Fair-rite 2743001111 PTH Dale Inductor IM-4-1.0uH PTH PNP Signal Transistor TO-92 PTH NPN Signal Transistor TO-92 PTH 10K Ohm/1206/5% 182 Ohm/PTH/1% 1K Ohm/1206/5% 39 Ohm/1206/5% 150 Ohm/1206/5% 15K Ohm/1206/5% 100K Ohm/1206/5% 100K Ohm/Trim POT Spectrol 63S104T607 or equivalent 470K Ohm/1206/5% 200K Ohm/Trim POT Spectrol 63S204T607 or equivalent 14K Ohm/1206/1% Switch DIP 5 position QFP15-128/128 pin
C1-C12, C15-C18 0.01uF C20, C21, C30 C23-C25 C22, C26, C27 C29 D7 D1-D6 JP1-JP3 H1, H2 J5 J6 L1-L5, L7-L9 L6 Q1 Q2 R10-R16, R18R19 R27 R26, R33-R34 R17, R20-R22, R28-R29 R23-R25 R2-R9 R1, R35-R36 R37 R30 R31 R32 S1 U1 0.1uF 10uF/63V 56uF/35V 33uF LM385BZ-1.2 1N4148 .1 x 3 Male Header CON34A Male Header PS/2 CONNECTOR CON40A Ferrite Bead 1uH 2N3906 2N3903 10K 182 1K 39 150 15K 100K 100K 470K 200K 14K SW-DIP-5 SED1354F0A
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 19
Item # Qty/board 30 31 32 33 34 35 36 37 1 1 1 1 1 1 1 1 U2 U3 U4 U5 U6 U7 U8 U9
Designation
Part Value UPD4218S165LE-50 TIBPAL22V10-15BCNT Osc. -14 74LS125 BT481A RD-0412 EPN001 LP2960AIN-3.3
Description NEC 1Mx16 , EDO, Self-Refresh, DRAM, SOJ package Texas Instrument PAL 24 pin DIP package/socketed Fox 40.0MHz Oscillator or equiv. 14 pin DIP/socketed 14 pin SO-14 package BrookTree RAMDAC PLCC package, 44-pin PLCC SMT part XENTECK - Positive Power Supply XENTECK - Negative Power Supply National 3.3V Fixed Voltage Regulator N16G 16-PIN DIP package
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
SED1354 X19A-G-004-05
Page 20
SED1354 X19A-G-004-05
2 3 4 5 6 7 8
1
SA[0..19] U1
SA[0..19] MA[0..8] MA[0..8]
A
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9/GPIO3 MA10/GPIO1 MA11/GPIO2 MD[0..15] MD[0..15] MA9 MA10 MA11
40 38 36 34 35 37 39 41 43 45 42 44 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8
A
A20 SD[0..15] SD[0..15]
8 Schematic Diagrams
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 A20 AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 66 64 62 60 58 56 54 52 53 55 57 59 61 63 65 67 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15
3 2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111
B
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 RAS# LCAS# UCAS# WE# 47 50 49 48 RAS# LCAS# UCAS# WE# LCDPWR RD/WR# WE1# WE0# RD# BS# FPFRAME FPLINE FPSHIFT MOD/DRDY/FPSHIFT2 FPDAT[0..7] 69 70 73 72 RESET# M/R# CS# BUSCLK CLKI 71 LCDPWR#
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
B
RD1# WE1# WE0# RD0# BS# RESET# M/R# CS# BUSCLK CLKI 13 WAIT# 105 108 4 5 FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 75 76 77 78 79 80 81 82 11
10 9 8 7 6
FPFRAME FPLINE FPSHIFT MOD/DRDY/F FPDAT[0..7]
PSHIFT2
FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7
FPD AT[8..15]
FPD AT[8..15]
C
C
READY R1 IOVDD 100K 106 SUSPEND #/GPO TESTEN DACP0/GPIO6 COREVDD COREVDD DACCLK 98 86 107 12 GPIO0 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15
88 89 90 91 92 93 94 95 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15
DACP0 DACCLK
Figure 1: SED1354B0C Schematic Diagram (1 of 6)
3.3V 33 97 IOVDD 14 46 83 110 IOVDD IOVDD IOVDD IOVDD HRTC/GPIO10 VRTC/GPIO11 BLANK#/GPIO5 DACRD#/GPIO4 DACWR#/GPIO7 DACRS0/GPIO8 DACRS1/GPIO9 102 103 85 84 99 100 101 HRTC VRTC BLANK# DACRD# DACWR# DACRS0 DACRS1 3.3V 15 32 51 68 74 87 96 104 109 VSS VSS VSS VSS VSS VSS VSS VSS VSS +12V VCC SED1354F0A VSS Size B Date:
2 3 4 5 6
D
3.3V
D
+12V
EPSON RESEARCH AND DEVELOPMENT, INC. SDU1354B0C ISA-Bus Rev. 1.0 Evaluation Board Document Number Rev 1.0 Monday, September 29, 1997
7
VCC
GND
Sheet
1
8
of
6
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
1
1
2
3
4
5
6
7
8
MD[0..15] VCC MA[0..8]
MD[0..15]
MD[0..15]
MA[0..8]
U2
A
A
R2 15K S1 MD1 MD2 MD3 MD4 MD5 SW DIP-5 1 2 3 4 5 10 9 8 7 6 15K 15K 15K 15K 15K
R3
R4
R5
R6
R7
R8 15K
R9 15K
Epson Research and Development Vancouver Design Center
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 A0 A1 A2 A3 A4 A5 A6 A7 A8R/A8 A9R/A9 A10/NC A11/NC /RAS /UCAS /LCAS /W VCC C1 .01 C2 .01 C3 .01 NC NC NC /OE uPD4218 165LE-50 VSS VSS VSS 22 37 42 VCC VCC VCC 1 6 21 MD6 MD9 MD10
MA9 MA10 MA11 14 30 31 13 11 12 32 29
17 18 19 20 23 24 25 26 27 28 16 15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15
RAS# UCAS# LCAS#
2 3 4 5 7 8 9 10 33 34 35 36 38 39 40 41
WE#
JP1 HEADER 3 LA[17..23] SA[0..19] U3
LA[17..23]
SA[0..19]
3 2 1
U4 1 NC OUT 40.0Mhz Oscillator GND 7 C5 .01 VCC CLKI 8 14 VCC 2
1
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
B
B
BS#
IOVDD
LA23 LA22 LA21 LA20 SA0 MEMSEL CLK/IN IN IN IN IN IN IN IN IN IN IN GND TIBPAL22V10 C4 .01 VCC 24 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN
RESET#
C
BALE /MEMR /MEMW /SBHE /REFRESH RESET 12
1 2 3 4 5 6 7 8 9 10 11
23 22 21 20 19 18 17 16 15 14 13
CS# M/R# A20 WE1# WE0# RD1# RD0#
C
Figure 2: SED1354B0C Schematic Diagram (2 of 6)
VCC R10 10K 3 /MEMCS16 U5A 74LS125 3.3V +12V VCC VSS Size B Date:
2 3 4 5 6
D
D
3.3V
+12V
EPSON RESEARCH AND DEVELOPMENT, INC. SDU1354BOC ISA-BUS Rev. 1.0 Evaluation Board Document Number Rev 1.0 Tuesday, September 30, 1997
7
VCC
GND
Sheet
2
8
of
6
SED1354 X19A-G-004-05
1
Page 21
Page 22
SED1354 X19A-G-004-05
2 3 4 5 6 7 8
1
VCC
SD[0..15] VCC VCC J1 J2 RESET
SD[0..15]
R11 10K
A
A
R12 10K
SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 +12V
READY
/REFRESH R13 VCC 10K BALE
B
BUSCLK
B
SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 AT CON-A SA[0..19] LA[17..23] J3 J4 VCC R14 VCC 10K R15 10K R16 10K LA23 LA22 LA21 LA20 LA19 LA18 LA17 VCC AT CON-B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 /IOCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 GND RESET +5V IRQ9 -5V DRQ2 -12V OWS +12V GND /SMEMW /SMEMR /IOW /IOR /DACK3 DRQ3 /DACK1 DRQ1 /REFRESH CLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 /DACK2 T/C BALE +5V OSC GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SA[0..19]
LA[17..23]
/SBHE
/MEMCS16
/MEMR /MEMW
C
SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 AT CON-C JP2 3.3V IOVDD VCC C6 .01 C7 .01 C8 .01 C9 .01 IOVDD By-pass Capacitors (1/power pin) 3.3V AT CON-D
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 /SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 /MEMR /MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 VCC /MEMCS16 /IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 /DACK0 DRQ0 /DACK5 DRQ5 /DACK6 DRQ6 /DACK7 DRQ7 +5V MASTER GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
C
COREVDD By-pass Capacitors (1/power pin)
Figure 3: SED1354B0C Schematic Diagram (3 of 6)
3 2 1 HEADER 3 C10 .01 C11 .01 By-pass Capacitors (1/power pin) VCC C12 .01 3.3V VCC +12V +12V VCC + C13 10uF + C14 10uF VSS Size B Date:
2 3 4 5 6
D
3.3V
D
+12V
EPSON RESEARCH AND DEVELOPMENT, INC. SDU1354B0B ISA-Bus Rev. 1.0 Evaluation Board Document Number Rev 1.0 Tuesday, September 30, 1997
7
VCC
GND
Sheet
3
8
of
6
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
1
1
2
3
4
5
6
7
8
FAI R-RITE 2743001111 FERR OXCUBE VK20019-4B PHILL IPS 431202036690
L1 VCC FERRITE BEAD 1 2
PLACE CLOSE TO RAMDAC AVCC PINS AVCC
A
A
C15 .01 R17 DACCLK 39 FPD AT[8..15] L2 1 SD[0..15] U6 IOVDD R18 10K 1 R19 10K AVCC 2
C16 .01
C17 .01
C18 .01
+
C19 10uF Tantulum
Epson Research and Development Vancouver Design Center
FPD AT[8..15] DACP0 SD[0..15]
1
R20 6 16 R21 L3 17 18 19 RED GREEN BLUE AVCC AVCC 27 26 1 1 L5 2 L4 2 RS0 RS1 RS2 R22 BLANK# 39 COMP OPA VREF 31 30 29 C20 .1 R26 1K R23 150 1% R24 150 1% 25 1 39 /RD /WR CLK 40
39
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 D0 D1 D2 D3 D4 D5 D6 D7 1N4148 P0 P1 P2 P3 P4 P5 P6 P7 D1
8 9 10 11 12 13 14 15 DACP0 FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9
32 33 34 35 36 37 38 39
D2
1
D3 J5
DACRD# DACWR#
2
2
1
1
5 7 23 1 2 /SYNC /BLANK SETUP /SENSE 6*/8
R25 150 1%
D4 1N4148
D5
1
2
2
2
4 20 21 22 D7 IREF 3 R27 182 1% C21 .1 1 2 28 AVCC /TRUECOL AVCC AVCC GND GND BT481A 3 24
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
2 2
B
B
DACRS0 DACRS1
D6
41 42 43 44 OL0 OL1 OL2 OL3 AVCC
6 1 11 7 2 12 8 3 13 9 4 14 10 5 15
LM385BZ-1.2
Figure 4: SED1354B0C Schematic Diagram (4 of 6)
R28 HRTC VRTC R29 39 39 3.3V +12V VCC VSS Size B Date:
2 3 4 5 6
C
C
D
D
3.3V
+12V
EPSON RESEARCH AND DEVELOPMENT, INC. SDU1354B0C ISA-Bus Rev. 1.0 Evaluation Board Document Number Rev 1.0 Tuesday, September 30, 1997
7
VCC
GND
Sheet
4
8
of
6
SED1354 X19A-G-004-05
1
Page 23
Page 24
B
1 2 3
SED1354 X19A-G-004-05
2 3 4 5 6 7 8
1
FPDAT[0..7] COLOR/MONO LCD CONNECTOR FPD AT[8..15] J6
FPDAT[0..7]
A
FPD AT[8..15]
A
FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPSHIFT VLCD VCC +12V VDDH LCDPWR# FPLINE FPFRAME CON40A 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
MOD/DRDY/F
FPSHIFT PSHIFT2 FPLINE FPFRAME
B
JP3 HEADER 3
H1 SD0 SD2 SD4 SD6 SD8 SD10 SD12 SD14 RESET# +12V WE0# CS# WE1# HEADER 17X2 +12V READY M/R# VCC RD1# BUSCLK A20 SD13 SD15 SA14 SA16 SA18 SD9 SD11 SA8 SA10 SA12 SD5 SD7 SD1 SD3 SA0 SA2 SA4 SA6
H2 SA1 SA3 SA5 SA7 SA9 SA11 SA13 SA15 SA17 SA19 VCC BS# RD0#
Figure 5: SED1354B0C Schematic Diagram (5 of 6)
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 17X2 3.3V +12V VCC VSS Size B Date:
2 3 4 5 6
C
C
D
D
3.3V
+12V
EPSON RESEARCH AND DEVELOPMENT, INC. SDU1354B0C ISA-Bus Rev. 1.0 Evaluation Card Document Number Rev 1.0 Tuesday, Se ptember 30, 1997
7
VCC
GND
Sheet
5
8
of
6
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
1
1
2
3
4
5
6
7
8
U7 RD-0412
REMOTE
NC
VOUT_ADJ
DC_IN
2
3
GND GND GND GND GND GND GND
9
4 5 6 7 8 10 11
1
12
DC_OUT
A
A
L6 2 R30 470K 1uH 5 VDDH
PSVCC
Epson Research and Development Vancouver Design Center
C22 + 3 + R31 200K 2 C23 10uF/63V Low ESR + + C24 10uF/63V Low ESR C25 10uF/63V 56uF/35V
LCDPWR# 1
R32 14K
PSGND
B
B
PSIOVDD
3
VOUT_ADJ
NC NC NC NC
DC_OUT
DC_IN DC_IN
GND GND
DC_OUT
6
5 4
9 8 7 3
2
11 10
1
100K PSVCC 3 + C26 56uF/35V 2 L7 1 PSIOVDD 1 2 R37 100K + C27 56uF/35V Low ESR 1 3 Q2 2N3903 VLCD
C
2
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
R33 2 U8 EPN001 1K PSVCC Q1 2N3906 1 R34 1K R36 R35 100K
C
IOVDD L8 1 PSVCC 2
VCC L9 1 PSGND 2
Figure 6: SED1354B0C Schematic Diagram (6 of 6)
PSGND U9 VCC 3 14 15 C28 10uF Tantulum 3.3V 1 VIN FDBK VTAP N/C ERR N/C COUT VOUT SENS 6 7 10 11 16 CIN VREF SHTDN LP29 60AIN-3.3 +12V C29 33uF Tantulum 2 8 9 C30 .1uF VCC VSS Size B Date:
2 3 4 5 6
3.3V
D
D
3.3V
+12V
EPSON RESEARCH AND DEVELOPMENT, INC. SDU1354B0C ISA-Bus Rev. 1.0 Evaluation Board Document Number Rev 1.0 Monday, Sep tember 29, 1997
7
VCC
GND
Sheet
6
8
of
6
SED1354 X19A-G-004-05
1
Page 25
Page 26
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-004-05
SDU1354B0C Rev.1.0 ISA Bus Evaluation Board User Manual Issue Date: 98/10/29
ENERGY SAV ING
EPSON
SDU1354-D9000
Evaluation Board User Manual
Document Number: X19A-G-003-04
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 SED1354 Color Graphics LCD Controller . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 3 3.1 Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 LCD Display Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 CRT Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Adjustable LCD BIAS Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
D9000 Specifics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.3 3.4 3.5 Connector Pinout for Channel A6 and A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory Address (CS#, M/R#) Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Makefpga file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Board Dimensions
Support Documentation Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Parts List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Schematic Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5.1 3.5.2 3.5.3 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Component Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Perspective View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 2-1: Table 3-1: Table 3-2: Table 3-3: Table 3-4: LCD Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Connector Pinout for Channel A7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Connectors Pinout for Channel A6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DIP Switch Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
List of Figures
Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: SDU1354-D9000 Schematic Diagram (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SDU1354-D9000 Schematic Diagram (2 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 SDU1354-D9000 Schematic Diagram (3 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SDU1354-D9000 Schematic Diagram (4 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Component Placement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SDU1354-D9000 Perspective View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
The Hitachi D9000 Development System uses expansion boards to provide a means to interface peripherals to the FPGA / processor combination. This manual describes how the SDU1354-D9000 Evaluation Board is used to provide a color LCD solution for the Windows CE environment. Reference SED1354 Hardware Functional Specification, document number X19A-A-002-xx. D9000 Development System, Hardware User Manual - Hitachi.
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 8
Epson Research and Development Vancouver Design Center
2 Features
* SED1354 color graphics LCD / CRT controller. * On-board 2M byte EDO-DRAM display buffer. * 4/8-bit monochrome LCD interface. * 4/8/16-bit color LCD interface. * Single-panel / single-drive displays. * Dual-panel / dual-drive displays. * 9/12-bit TFT. * 18/24-bit TFT support to 64K colors (16-bit data). * CRT support. * On-board adjustable LCD BIAS voltage power supply. * SmallTypeZ x 2 form factor (requires two side-by-side SmallTypeZ slots).
2.1 SED1354 Color Graphics LCD Controller
The SED1354 is a low cost, low power color/monochrome LCD/CRT controller capable of interfacing to a wide range of CPUs and LCD displays. The SED1354 supports LCD interfaces with data widths up to 16 bits. Using Frame Rate Modulation (FRM), it can display 16 shades of gray on monochrome panels, up to 4096 colors on passive panels and 64K colors on active matrix TFTs. CRT support is handled through the use of an external RAMDAC allowing simultaneous display of both the CRT and LCD displays. In this design, the SED1354 has a 3.3V core voltage (Core VDD) and a 3.3V IO voltage (IO VDD). For complete details on register functionality and programming, refer to the SED1354 Hardware Functional Specification document number X19A-A-002-xx, and the Programming Notes and Examples, document number X19A-G-002-xx.
2.1.1 Display Buffer
The SED1354 supports a 512K byte or 2M byte, FPM-DRAM or EDO-DRAM display buffer. On the SDU1354-D9000 evaluation board, a 1Mx16 EDO-DRAM is used to provide adequate memory for all supported display resolutions, and when smaller display sizes are used, to provide multiple "pages" of memory. EDO-DRAM with self-refresh may also be used to provide the lowest possible power consumption during power save modes.
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 9
2.1.2 LCD Display Support
The SED1354 provides a wide range of flexibility for display type and resolution. Display types include: * 4/8-bit monochrome passive. * 4/8/16-bit color passive. * Active matrix TFT. * other (EL, REC, etc.). Display resolutions range from 4x1 to 800x600, with color depths from black and white to 64K colors. The LCD connector is a 50 pin AMPLIMITE Subminiature D Connector (P/N 787171-5) and has the signals shown in the following table "LCD Connector Pinout".
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 10
Epson Research and Development Vancouver Design Center
2.1.3 LCD Interface Pin Mapping
Table 2-1: LCD Connector Pinout
Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 40 41 42 43 44 45 46 47 48 49 50 2,4,6,8,10, 12,14,16,18,20, 22,24,26,28,30, 32,34,36,38 SED1354 Pin Names FPSHIFT DRDY FPLINE FPFRAME FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 LCDPWR LCDBACK# XY1 XL XR YU YL VDDH +5V +3.3V +12V B0 G0 R2 R1 R0 G2 G1 G0 B2 B1 B0 R3 R2 R1 G3 G2 G1 B3 B2 B1 R0 R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 G2 G1 G0 B2 B1 UD0 UD1 UD2 UD3 DRDY FPLINE FPFRAME LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 LD4 LD5 LD6 LD7 UD4 UD5 UD6 UD7 On/Off Control for LCD Power On/Off Control for Backlight Touch Screen input Touch Screen input Touch Screen input Touch Screen input Touch Screen input +30V LCDBIAS UD0 UD1 UD2 UD3 LD0 LD1 LD2 LD3 UD0 UD1 UD2 UD3 Color TFT 9-bit 12-bit 18-bit 4-bit Color Passive 8-bit 16-bit MOD/FPSHIFT2 FPSHIFT Mono Passive 4-bit 8-bit Comments
GND
Note 1. XY is the 5th signal for those touch panels that require 5 interface signals. When using 4-signal touch panels, remove jumper JP1 on the board to disconnect this signal.
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 11
2.1.4 CRT Support
The SED1354 has all the necessary signals to interface to an external RAMDAC so a CRT is supported. The Brooktree Bt481A RAMDAC is supported on the SDU1354-D9000 evaluation board. Refer to the Programming Notes and Examples, document number X19A-G-002-xx for programming details.
2.1.5 Adjustable LCD BIAS Power Supply
Most color 640x480 passive LCD panels require a positive power supply to provide between +23V and +40V (Iout = 45mA). For ease of implementation, such a power supply has been provided as an integral part of this design. The signal VDDH can be adjusted by R16 to provide an output voltage from +23V to +40V and is enabled / disabled by the SED1354 control signal LCDPWR. LCDPWR is an output signal which follows a pre-defined power-up / power-down sequence designed to protect the LCD panel from damage caused by the power supply being enabled in the absence of control signals. Determine the panel's specific power requirements and set the potentiometer accordingly before connecting the panel.
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 12
Epson Research and Development Vancouver Design Center
3 D9000 Specifics
3.1 Interface Signals
The SED1354 is intended for direct connection to most processors, so the FPGA in this environment simply acts as a pass-through for the required processor interface signals. Table 3-1: Interface Signals
Interface Signals SED1354 Signal Name AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BCLK BS# RD/WR# RD# WE0# WAIT# RESET# 5.0V 3.3V GND 12.0V XL XR YU YL XY Touch Screen Touch Screen Touch Screen Touch Screen Touch Screen Number of Signals 19 1 16 1 1 1 1 1 1 1 1 1 1 SH-3 Interface Signal Name A[20:1] A0 D[15:0] WE1# External Decode External Decode CKIO BS# RD/WR# RD# WE0# WAIT# RESET# Generic CPU Interface Signal Name A[20:1] A0 D[15:0] WE#1 External Decode External Decode BCLK nc RD1# RD0# WE0# WAIT# RESET# Memory / Register Select SED1354 Chip Select Bus Clock
Comments
Address Bus Address Bus Data Bus
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 13
3.1.1 Connector Pinout for Channel A6 and A7
Table 3-2: Connector Pinout for Channel A7
Channel A7 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FPGA Signal chA7p1 chA7p2 chA7p3 chA7p4 chA7p5 chA7p6 chA7p7 chA7p8 chA7p9 chA7p10 ib1 ib2 ib3 ib4 ib5 ib6 ib7 ib8 GND GND SED1354 Signal SmXY BCLK N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C GND GND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 dc5v GND dc3v GND dc3v GND dc3vs GND dc12v GND battery GND dcXA base5vDc dcXB GND dcXC GND senseH senseL DC5V GND DC3V GND DC3V GND N/C GND DC12V GND N/C GND N/C N/C N/C GND N/C GND N/C N/C Pin # FPGA Signal SED1354 Signal
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 14
Epson Research and Development Vancouver Design Center
Table 3-2: Connector Pinout for Channel A7 (Continued)
Channel A7 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FPGA Signal chA7p11 chA7p12 chA7p13 chA7p14 chA7p15 chA7p16 chA7p17 chA7p18 chA7p19 chA7p20 chA7p21 chA7p22 chA7p23 chA7p24 chA7p25 chA7p26 chA7p27 chA7p28 chA7p29 chA7p30 SED1354 Signal SmZ N/C N/C A20 A18 A17 A16 N/C A14 A13 A12 A11 A9 A8 A7 A6 A5 A3 A2 A1 A0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND GND chA7p34 GND GND GND chA7p33 GND GND GND chA7p32 GND GND GND GND chA7p31 GND GND GND GND GND GND A19 GND GND GND A15 GND GND GND A10 GND GND GND GND A4 GND GND GND GND Pin # FPGA Signal SED1354 Signal
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 15
Table 3-3: Connectors Pinout for Channel A6
Channel A6 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FPGA Signal chA6p1 chA6p2 chA6p3 chA6p4 chA6p5 chA6p6 chA6p7 chA6p8 chA6p9 chA6p10 ib1 ib2 ib3 ib4 ib5 ib6 ib7 ib8 GND GND SED1354 Signal SmXY CS# BS# WE0# RD/WR# WAIT# N/C N/C N/C N/C N/C XL XR YU YL N/C N/C N/C YL GND GND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 dc5v GND dc3v GND dc3v GND dc3vs GND dc12v GND battery GND dcXA base5vDc dcXB GND dcXC GND senseH senseL DC5V GND DC3V GND DC3V GND N/C GND DC12V GND N/C GND N/C N/C N/C GND N/C GND N/C N/C Pin # FPGA Signal SED1354 Signal
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 16
Epson Research and Development Vancouver Design Center
Table 3-3: Connectors Pinout for Channel A6 (Continued)
Channel A6 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 FPGA Signal chA6p11 chA6p12 chA6p13 chA6p14 chA6p15 chA6p16 chA6p17 chA6p18 chA6p19 chA6p20 chA6p21 chA6p22 chA6p23 chA6p24 chA6p25 chA6p26 chA6p27 chA6p28 chA6p29 chA6p30 SED1354 Signal SmZ M/R# RD# WE1# RESET# N/C N/C N/C D14 D13 D12 D11 D9 D8 D7 D6 D5 D3 D2 D1 D0 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND GND chA6p34 GND GND GND chA6p33 GND GND GND chA6p32 GND GND GND GND chA6p31 GND GND GND GND GND GND N/C GND GND GND D15 GND GND GND D10 GND GND GND GND D4 GND GND GND GND Pin # FPGA Signal SED1354 Signal
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 17
3.1.2 Bus Interface Timing
Refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx for complete bus timing details. Note A four-position DIP switch located on the SDU1354-D9000 allows for the following configurations. Table 3-4: DIP Switch Configuration
SW4 x x x x 0 1 SW3 0 0 0 0 x x SW2 0 0 1 1 x x SW1 0 1 0 1 x x Function SH-3 Bus Interface MC68K Bus 1 Interface MC68K Bus 2 Interface Generic Bus Interface WAIT# - active low WAIT# - active high
Where 1 = closed/on and 0 = open/off
3.1.3 Memory Address (CS#, M/R#) Decode
The SED1354 is a memory-mapped device for both the registers and display buffer access. The specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space requirements are: * a 2M byte linear address range for the display buffer * 47 bytes for the registers.
3.1.4 Makefpga file
Modifications to the makefpga file to accommodate the SED1354 are: 1. 2. Bus model: this may differ depending on processor as far as interface requirements (signal definitions). Epson will provide this information for each given processor interface. Memory location: the system designer must determine the appropriate memory addresses for the display buffer and register requirements.
3.2 Board Dimensions
To obtain the required number of interface signals, the SDU1354-D9000 utilizes two SmallTypeZ slots (6 and 7). Board dimensions are 2.65x3.20 with both the CRT and LCD connectors accessible on the outside edge.
3.3 Support Documentation Notes
Note that some files and/or documentation may refer to the SDU1354-D9000 as the SDU1354D9100.
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 18
Epson Research and Development Vancouver Design Center
3.4 Parts List
Item #
Qty.
Reference C1,C2,C3,C4,C5,C6,C7, C8,C9,C11,C12,C13,C14, C15,C16,C21,C26,C27, C28,C29,C34,C35,C36, C37 C10 C17 C18,C19,C20 C22,C23,C24,C25,C30, C31,C32,C33 D1,D2,D3 JP1 JP2,JP3,JP4,JP5 J1 J2 L1,L2,L3,L4,L5 L6 R1,R2,R3,R4,R5,R6,R7, R8,R17 R9,R10,R11 R12,R13 R14 R15 R16 R18, R19, R20 S1 U1 U2 U3 U4 U5 JP1
Part
Description
1
24
0.1uF
0.1uF, 0805 pckg
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 1 3 8 3 1 4 1 1 5 1 9 3 2 1 1 1 3 1 1 1 1 1 1 1
10uF 56uF/35V 10uF/63V 22uF BAV99 Header 2 Header 2x20 PS/2 CONNECTOR LCD CON INDUCTOR 1uH 15K 150 1% 39 182 1% 470K 200K 10K SW DIP-4 SED1354F0A BT481A RD-0412 OSC-8 Micro Shunt
10uF / 20V Tantalum C-Size Electrolytic, Radial Lead 35V +/- 20% Nippon / United Chemi-Con LXV35VB56RM6X11LL or equivalent Electrolytic, Radial Lead 63V +/- 20% Nippon / United Chemi-Con KMF63VB10RM5X11LL or equivalent 22uF / 20V Tantalum D-Size SMT / SOT-23 pckg 1x2, .025" sq. Header 2x20, .05"x.05" Micro Strips Samtec TFM-120-11-S-D DB15, Female, Vertical, Board Mount AMP 749374-3 Subminiature D, 50-pin, Receptacle Header, Right Angle, Board Mount AMP 787171-5 Ferrite Bead Fair-rite 2743001111 1uH Dale Inductor IM-4-1.0uH 15K ohm, 0805 pckg, 5% 150 ohm, 0805 pckg, 1% 39 ohm, 0805 pckg, 5% 182 ohm, 0805 pckg, 1% 470K ohm, 0805 pckg, 5% Trim Pot, 4mm Sq., Single Turn, SMT Bourns 3314J-1204 or BI Technologies 23AR200K 10K ohm, 0805 pckg, 5% SMT Dip Switch, 4 Position CTS 219-4LPST or Grayhill 90HBW04S QFP15-128 Epson SED1354F0A RAMDAC, PLCC pckg Brooktree BT481A Positive Power Supply XENTECK RD-0412 Half Size Clock Oscillator, 8-Pin, 40MHz Digi-Key P/N CTX175-ND or equivalent
DRAM1MX16-SOJ 1Mx16 EDO, 60ns, SOJ pckg Micron MT4C1M16E5DJ-6
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
1
2
3
4
5
6
7
8
A[0..20] MA[0..9]
A[0..20]
U1 MA[0..9]
Epson Research and Development Vancouver Design Center
3.5 Schematic Diagrams
Evaluation Board User Manual Issue Date: 98/10/29
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9/GPIO3 MA10/GPIO1 MA11/GPIO2 MD[0..15] MD[0..15] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 D[0..15] AB0 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 66 64 62 60 58 56 54 52 53 55 57 59 61 63 65 67 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 3 2 1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 40 38 36 34 35 37 39 41 43 45 42 44 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9
D
D
D[0..15]
C
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15 RAS# LCAS# UCAS# WE# 47 50 49 48 RAS# LCAS# UCAS# WE# LCDPWR RD/WR# WE1# WE0# RD# BS# FPFRAME FPLINE FPSHIFT MOD/DRDY/FPSHIFT2 69 70 73 72 FPDAT[0..15] RESET# M/R# CS# BUSCLK CLKI WAIT# GPIO0 SUSPEN D#/GPO TESTEN 71 10 9 8 7 6 11 5 4 108 105 13 12 LCDPWR# FPFRAME FPLINE FPSHIFT FPSHIFT2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C
RD/WR# WE1# WE0# RD# BS# RESET# M/R# CS# BCLK CLKI FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 75 76 77 78 79 80 81 82
FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7
FPDAT[0..15]
WAIT#
B
106 107
B
LCDBACK#
FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 DACP0/GPIO6
88 89 90 91 92 93 94 95 98 DACCLK 86
FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 DACP0 DACCLK
DC3V C1 0.1uF DC3V 14 46 83 110 C3 0.1uF C4 0.1uF C5 0.1uF C6 0.1uF 15 32 51 68 74 87 96 104 109 C2 0.1uF
Figure 3-1: SDU1354-D9000 Schematic Diagram (1 of 4)
33 97 COREVDD COREVDD IOVDD IOVDD IOVDD IOVDD HRTC/GPIO10 VRTC/GPIO11 BLANK#/GPIO5 DACRD#/GPIO4 DACWR#/GPIO7 DACRS0/GPIO8 DACRS1/GPIO9 102 103 85 84 99 100 101 HRTC VRTC BLANK# DACRD# DACWR# DACRS0 DACRS1 VSS VSS VSS VSS VSS VSS VSS VSS VSS SED1354F0A Size B Date:
A
A
EPSON RESEARCH AND DEVELOPMENT INC. Title
SDU1354-D9000
Document Number
Rev 1.0 Sheet 1 of 4
SDU1354-D9000 X19A-G-003-04
2
1
3
4
5
6
Friday, J uly 25, 1997 7
8
Page 19
Page 20
2
2
D[0..15]
D[0..15] U3
D1 BAV99
D2 BAV99
2
1
1
DACRD# DACWR# DACRS0 DACRS1 GREEN BLUE C12 COMP OPA 0.1uF 31 C13 0.1uF IREF 28 R14 182 1% VREF 41 42 43 44 OL0 OL1 OL2 OL3 AVCC /TRUECOL AVCC AVCC GND GND BT481A AVCC 4 20 21 22 C14 0.1uF 3 24 C15 0.1uF C16 0.1uF 30 29 AVCC 27 R9 150 1% R10 150 1% 26 17 18 19 RS0 RS1 RS2 RED 25
6 16 /RD /WR CLK
40 L3 L4 L5 R11 150 1%
1
SDU1354-D9000 X19A-G-003-04
2 3 4 5 6 7 8
DC5V MD[0..15] MA[0..9] S1 MD1 MD2 MD3 MD5 SW DIP-4 MD4 MD6 MD9 MD10 1 2 3 4 8 7 6 5 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 A0 A1 A2 A3 A4 A5 A6 A7 A8R/A8 A9R/A9 A10/NC A11/NC /RAS /UCAS /LCAS /W NC NC NC C7 0.1uF L1 DC5V + C11 0.1uF C8 0.1uF C9 0.1uF /OE DRAM1MX16-SOJ VSS VSS VSS 22 37 42 VCC VCC VCC 1 6 21 DC5V 17 18 19 20 23 24 25 26 27 28 16 15 14 30 31 13 11 12 32 29 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 2 3 4 5 7 8 9 10 33 34 35 36 38 39 40 41 MA[0..9] U2 R1 15K R2 15K R3 15K R4 15K R5 15K R6 15K R7 15K R8 15K MD[0..15]
1
D
D
RAS# UCAS# LCAS# WE#
L2 AVCC C10 10uF
C
C
DACCLK FPDAT[0..15] DACP0 FPDAT[0..15]
AVCC
D3 BAV99
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT11 FPDAT10 FPDAT9 P0 P1 P2 P3 P4 P5 P6 P7
8 9 10 11 12 13 14 15
32 33 34 35 36 37 38 39
3
3
3
J1
B
B
BLANK#
5 7 23 1 2 /SYNC /BLANK SETUP /SENSE 6*/8
R12 R13
39 39
Figure 3-2: SDU1354-D9000 Schematic Diagram (2 of 4)
6 1 11 7 2 12 8 3 13 9 4 14 10 5 15 HRTC VRTC Size B Date:
PS/2 CONNECT OR
A
A
EPSON RESEARCH AND DEVELOPMENT INC. Title
SDU1354-D9000 Document Number
Rev 1.0 Sheet 2 of 4
Epson Research and Development Vancouver Design Center
Evaluation Board User Manual Issue Date: 98/10/29
2 3
1
4
5
6
Friday, J uly 25, 1997 7
8
1
2
3
4
5
6
7
8
U4 RD-0412
REMOTE
NC
VOUT_ADJ
DC_IN
GND GND GND GND GND GND GND
DC_OUT
Epson Research and Development Vancouver Design Center
2
3
9
4 5 6 7 8 10 11
1
12
Figure 3-3: SDU1354-D9000 Schematic Diagram (3 of 4)
FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 JP1 XY EN 1 2
Evaluation Board User Manual Issue Date: 98/10/29
D
L6 DC5V LCDPWR# 1uH R15 470K VDDH R16 + 200K C17 56uF/35V + C18 10uF/63V + C19 10uF/63V + C20 10uF/63V R17 15K C FPDAT[0..15] FPSHIFT FPSHIFT2 FPLINE FPFRAME FPDAT[0..15] J2 U5 1 CLKI 5 NC OUT 40MHz VCC GND 8 4 DC5V C21 0.1uF
D
C
B
B
LCDBACK# XL YU VDDH DC3V LCD CON DC5V DC12V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LCDPWR# XY XR YL
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
A
EPSON RESEARCH AND DEVELOPMEN T INC. Title SDU1354-D9000 Size B Date: Document Number Sheet 3 of 4 Rev 4.0
SDU1354-D9000 X19A-G-003-04
2
1
3
4
5
6
Monday, August 25, 1997 7
8
Page 21
Page 22
SDU1354-D9000 X19A-G-003-04
2
1
6 7
3
4
5
8
D DC3V R20 10K JP2 JP3 DC5V DC3V CS# BS# WE0# RD/WR# WAIT# D15 10K R18 DC3V
D
D[0..15]
D[0..15]
M/R# RD# WE1# RESET# R19 10K D10 XL XR YU YL + C25 10uF C26 0.1uF + C22 4.7uF
DC12V + C23 4.7uF + C24 10uF
D4 XY
C27 0.1uF
C28 0.1uF
C29 0.1uF C
C
D14 D13 D12 D11 D9 D8 D7 D6 D5 D3 D2 D1 D0 A11_SmZ A11_SmXY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A[0..20] JP4 JP5 A19 BCLK
A[0..20]
DC5V DC3V
A20 A18 A17 A16 A15
A10
DC12V + + C33 10uF C34 0.1uF C30 4.7uF + C31 4.7uF + C32 10uF B
B
A14 A13 A12 A11 A9 A8 A7 A6 A5 A3 A2 A1 A0 A4 A10_SmZ
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A10_SmXY
Figure 3-4: SDU1354-D9000 Schematic Diagram (4 of 4)
C35 0.1uF Size B Date:
C36 0.1uF
C37 0.1uF
A
A
EPSON RESEARCH AND DEVELOPMEN T INC. Titl e SDU1354-D9000 Document Number Sheet 3 4 5 4 of 4 Rev 4.0
Epson Research and Development Vancouver Design Center
Evaluation Board User Manual Issue Date: 98/10/29
2
1
6
Monday, August 25, 1997 7
8
Epson Research and Development Vancouver Design Center
Page 23
3.5.1 PCB Layout 3.5.2 Component Placement
Figure 3-5: Component Placement
Evaluation Board User Manual Issue Date: 98/10/29
SDU1354-D9000 X19A-G-003-04
Page 24
Epson Research and Development Vancouver Design Center
3.5.3 Perspective View
SED1354 LCD Power Supply RAMDAC CRT Connector DRAM
LCD Connector
Figure 3-6: SDU1354-D9000 Perspective View
SDU1354-D9000 X19A-G-003-04
Evaluation Board User Manual Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
Power Consumption
Document Number: X19A-G-006-03
Copyright (c) 1997, 1998 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-006-03
Power Consumption Issue Date: 98/10/29
Epson Research and Development Vancouver Design Center
Page 3
1 SED1354 Power Consumption
SED1354 power consumption is affected by many system design variables. * Input clock frequency (CLKI): the CLKI frequency determines the LCD frame-rate, CPU performance to memory, and other functions - the higher the input clock frequency, the higher the frame-rate, performance and power consumption. * CPU interface: the SED1354 IO VDD current consumption depends on the BUSCLK frequency, data width, number of toggling pins, and other factors - the higher the BUSCLK, the higher the CPU performance and power consumption. * Core VDD, IO VDD voltage levels: the voltage levels of the two independent VDD groups (Core, IO) affect power consumption - the higher the voltage, the higher the consumption. * Display mode: the resolution and color depth affect power consumption - the higher the resolution/color depth, the higher the consumption. * Internal CLK divide: internal registers allow the input clock to be divided before going to the internal logic blocks - the higher the divide, the lower the power consumption.
There are two power save modes in the SED1354: Software and Hardware SUSPEND. The power consumption of these modes is also affected by various system design variables. * DRAM refresh mode, CBR or self-refresh: self-refresh capable DRAM allows the SED1354 to disable the internal memory clock thereby saving power. * CPU bus state during SUSPEND: the state of the CPU bus signals during SUSPEND has a substantial effect on power consumption. An inactive bus (e.g. BUSCLK = low, Addr = low etc.) reduces overall system power consumption. * CLKI state during SUSPEND: disabling the CLKI during SUSPEND has substantial power savings.
Power Consumption Issue Date: 98/10/29
SED1354 X19A-G-006-03
Page 4
Epson Research and Development Vancouver Design Center
1.1 Conditions
The Table 1-1: "SED1354 Total Power Consumption" below gives an example of a particular environment and its effects on power consumption.
Table 1-1: SED1354 Total Power Consumption
Test Condition
Core VDD = 3.3V IO VDD = 5.0V ISA Bus (8MHz)
Total Power Consumption Gray Shades / Colors Power Save Mode Active Software 38.7mW 43.9mW 46.8mW 44.4mW 49.7mW 51.2mW 113.3mW 124.6mW 145.6mW 150.6mW 150.0mW 20mW1 Hardware 7.59uW2
1
Input Clock = 6MHz Black-and-White LCD Panel Connected = 320x240 Monochrome 4 Grays 16 Grays Input Clock = 6MHz LCD Panel Connected = 320x240 Color 4 Colors 16 Colors 256 Colors
2
20mW1
7.59uW2
3
Input Clock = 25MHz Black-and-White LCD Panel Connected = 640x480 Monochrome 16 Grays Input Clock = 25MHz LCD Panel Connected = 640x480 Color 16 Colors 256 Colors 64K Colors
24mW1
7.59uW2
4
24mW1
7.59uW2
Note 1. Conditions for Software SUSPEND: * CPU interface active (signals toggling) * CLKI active (6MHz) * Self-Refresh DRAM 2. Conditions for Hardware SUSPEND: * CPU interface inactive (high impedance) * CLKI stopped * Self-Refresh DRAM
2 Summary
The system design variables in Section 1, "SED1354 Power Consumption" and in Table 1-1: "SED1354 Total Power Consumption" show that SED1354 power consumption depends on the specific implementation. Active Mode power consumption depends on the desired CPU performance and LCD frame-rate, whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state. In a typical design environment, the SED1354 can be configured to be an extremely power-efficient LCD Controller with high performance and flexibility.
SED1354 X19A-G-006-03
Power Consumption Issue Date: 98/10/29
SED1354 Color Graphics LCD/CRT Controller
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Document Number: X19A-G-005-07
Copyright (c) 1998, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interfacing to the PR31500/PR31700 . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SED1354 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . 9 3.2 Generic MPU Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . 10 Direct Connection to the Philips PR31500/PR31700 . . 4.1 Hardware Description . . . . . . . . . . . . . . 4.2 Memory Mapping and Aliasing . . . . . . . . . . 4.3 SED1354 Configuration . . . . . . . . . . . . . System Design Using the IT8368E PC Card Buffer 5.1 Hardware Description--Using One IT8368E . . . 5.2 Hardware Description--Using Two IT8368E's . . 5.3 IT8368E Configuration . . . . . . . . . . . . 5.4 Memory Mapping and Aliasing . . . . . . . . 5.5 SED1354 Configuration . . . . . . . . . . . ... .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. ... .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. ... .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 14 14 17 18 19 20
4
5
6 7
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Technical Support . . . . . . . . . . . . . . 8.1 EPSON LCD/CRT Controllers (SED1354) . 8.2 Philips MIPS PR31500/PR31700 Processor . 8.3 ITE IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . 23 23 23 23
8
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 3-1: Table 4-1: Table 4-2: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . SED1354 Configuration for Direct Connection . . . . . . . . . . . . . . . . SED1354 Host Bus Selection for Direct Connection . . . . . . . . . . . . . PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping . PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E SED1354 Configuration using the IT8368E . . . . . . . . . . . . . . . . . . SED1354 Host Bus Selection using the IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 13 13 19 19 20 20
List of Figures
Figure 4-1: Typical Implementation of SED1354 to PR31500/PR31700 Direct Connection . . . . . 11 Figure 5-1: SED1354 to PR31500/PR31700 Connection using One IT8368E . . . . . . . . . . . . . 15 Figure 5-2: SED1354 to PR31500/PR31700 Connection using Two IT8368E. . . . . . . . . . . . . 17
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an interface between the SED1354 Color Graphics LCD/CRT Controller and the Philips MIPS PR31500/PR31700 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 8
Epson Research and Development Vancouver Design Center
2 Interfacing to the PR31500/PR31700
The Philips PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the SED1354 connects to the PR31500/PR31700 processor. The SED1354 can be successfully interfaced using one of three configurations: * Direct connection to PR31500/PR31700 (see Section 4, "Direct Connection to the Philips PR31500/PR31700" on page 11). * System design using one ITE8368E PC Card/GPIO buffer chip (see Section 5.1, "Hardware Description--Using One IT8368E" on page 14). * System design using two ITE8368E PC Card/GPIO buffer chips (see Section 5.2, "Hardware Description--Using Two IT8368E's" on page 17).
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 9
3 SED1354 Host Bus Interface
The SED1354 implements a 16-bit Generic MPU host bus interface which is used to interface to the Philips PR31500/PR31700 processor. The Generic MPU host bus interface is the least processor-specific interface mode supported by the SED1354 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the SED1354 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic `1', meaning that the SED1354 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal. Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 10
Epson Research and Development Vancouver Design Center
3.2 Generic MPU Host Bus Interface Signals
The interface requires the following signals: * BUSCLK is a clock input which is required by the SED1354 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. * The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset. * M/R# (memory/register) may be considered an address line, allowing system address A21 to be connected to the M/R# line. * Chip Select (CS#) must be driven low whenever the SED1354 is accessed by the host CPU. * WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * RD# (RD0#) and RD/WR# (RD1#) are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * WAIT# is a signal output from the SED1354 that indicates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the SED1354 may occur asynchronously to the display update, it is possible that contention may occur in accessing the SED1354 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. * The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and should be tied low (connected to GND).
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 11
4 Direct Connection to the Philips PR31500/PR31700
4.1 Hardware Description
The SED1354 is easily interfaced to the Philips PR31500/PR31700 processor. In the direct connection implementation, the SED1354 occupies PC Card slot #1 of the PR31500/PR31700. Although the address bus of the PR31500/PR31700 is multiplexed, it can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373). The direct connection implementation makes use of the Generic MPU host bus interface capability of the SED1354. The following diagram demonstrates a typical implementation of the PR31500/PR31700 to SED1354 interface.
SED1354 PR31500/PR31700 /RD /WE /CARD1CSL /CARD1CSH
+3.3V
IO VDD, CORE VDD RD0# RD1# WE0# WE1#
CS#
Latch
A23
System RESET
M/R# RESET# AB[20:13] AB[12:0] DB[7:0] DB[15:8]
ALE A[12:0] D[31:24] D[23:16] /CARD1WAIT
ENDIAN
A[20:13]
VDD
15K pull-up
See text
Clock divider
WAIT# BUSCLK CLKI
DCLKOUT
...or...
Oscillator
Note: When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of SED1354 to PR31500/PR31700 Direct Connection
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 12
Epson Research and Development Vancouver Design Center
The host interface control signals of the SED1354 are asynchronous with respect to the SED1354 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum SED1354 clock frequencies. The SED1354 also has internal clock dividers providing additional flexibility.
4.2 Memory Mapping and Aliasing
The SED1354 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the registers. This is divided into two address ranges by connecting A23 (demultiplexed from the PR31500/PR31700) to the M/R# input of the SED1354. Using A23 makes this implementation software compatible with the two implementations that use the ITE IT8368E (see Section 5, "System Design Using the IT8368E PC Card Buffer" on page 14). All other addresses are ignored. The SED1354 address ranges, as seen by the PR31500/PR31700 on the PC Card slot 1 memory space, are as follows: * 6400 0000h: SED1354 registers aliased 131,072 times at 64 byte intervals over 8M bytes. * 6480 0000h: SED1354 display buffer aliased 4 times at 2M byte intervals over 8M bytes. * 6500 0000h: SED1354 registers and display buffer, aliased another 3 times over 48M bytes. Since the PR31500/PR31700 control signal /CARDREG is ignored, the SED1354 takes up the entire PC Card slot 1 configuration space. The address range is software compatible with both ITE IT8368E implementations. * 0900 0000h: SED1354 registers aliased 131,072 times at 64 byte intervals over 8M bytes. * 0980 0000h: SED1354 display buffer aliased 4 times at 2M byte intervals over 8M bytes.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 13
4.3 SED1354 Configuration
The SED1354 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Specification, document number X19A-A-002-xx. The partial table below shows those configuration settings relevant to the direct connection implementation. Table 4-1: SED1354 Configuration for Direct Connection
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 Little Endian WAIT# signal is active high Big Endian WAIT# signal is active low See "Host Bus Selection" table below See "Host Bus Selection" table below value on this pin at rising edge of RESET# is used to configure:(1/0) 1 8-bit host bus interface 0 16-bit host bus interface
= required configuration for direct connection with PR31500/PR31700
Table 4-2: SED1354 Host Bus Selection for Direct Connection
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MCF5307, ISA bus interface) Reserved
= required configuration for direct connection with PR31500/PR31700
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 14
Epson Research and Development Vancouver Design Center
5 System Design Using the IT8368E PC Card Buffer
If the system designer uses an ITE IT8368E PC Card and multiple-function IO buffer, the SED1354 can be interfaced with the PR31500/PR31700 without using a PC Card slot. Instead, the SED1354 is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the SED1354 virtually transparent to PC Card devices that use the same slot.
5.1 Hardware Description--Using One IT8368E
The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers. The IT8368E provides eleven Multi-Function IO pins (MFIO). Configuration registers can be used to allow these MFIO pins to provide the control signals required to implement the SED1354 CPU interface. The Philips PR31500/PR31700 processor only provides addresses A[12:0], therefore devices that occupy more address space must use an external device to latch A[25:13]. The IT8368E's MFIO pins can be configured to provide this latched address. However, when using the SED1354, five MFIO pins are utilized for SED1354 control signals and cannot provide latched addresses. In this case, an external latch must be used to provide the highorder address bits. For a solution that does not require a latch, refer to Section 5.2, `Hardware Description--Using Two IT8368E's".
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 15
PR31500/PR31700
A[12:0]
ENDIAN
SED1354
+3.3V
IO VDD, CORE VDD AB[12:0]
ALE D[31:24] D[23:16]
Latch
AB[20:13] DB[7:0] DB[15:8]
System RESET pull-up
VDD
RESET# WAIT#
/CARDxWAIT DCLKOUT A23 See text
Clock divider
M/R# CLKI BUSCLK WE1# WE0# RD1# RD0#
IT8368E
LHA23/MFIO10 LHA22/MFIO9 LHA21/MFIO8 LHA20/MFIO7 LHA19/MFIO6
...or... Oscillator
Chip Select Logic
CS#
Notes: The Chip Select Logic shown above is necessary to guarantee timing parameter t1 of the Generic MPU Interface Asynchronous Timing (for details refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx). When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 5-1: SED1354 to PR31500/PR31700 Connection using One IT8368E
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 16
Epson Research and Development Vancouver Design Center
The Generic MPU host interface control signals of the SED1354 are asynchronous with respect to the SED1354 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum SED1354 clock frequencies. The SED1354 also has internal clock dividers providing additional flexibility.
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 17
5.2 Hardware Description--Using Two IT8368E's
The following implementation uses a second IT8368E, not in VGA mode, in place of an address latch. The pins LHA23 and LHA[20:13] provide the latch function instead.
PR31500/PR31700
A[12:0]
ENDIAN
SED1354
AB[12:0] AB[20:13]
D[31:24] D[23:16]
System RESET VDD pull-up
DB[7:0] DB[15:8] RESET# WAIT# LHA23
Clock divider
/CARDxWAIT DCLKOUT
M/R#
IT8368E
...or... Oscillator BUSCLK
LHA[20:13], LHA23
See text
CLKI
+3.3V
IO VDD, CORE VDD IT8368E LHA23/MFIO10 LHA22/MFIO9 LHA21/MFIO8 LHA20/MFIO7 LHA19/MFIO6 WE1# WE0# RD1# RD0# CS#
Chip Select Logic
Notes: The Chip Select Logic shown above is necessary to guarantee the timing parameter t1 of the Generic MPU Host Bus Interface Asynchronous Timing (for details refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx). When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 5-2: SED1354 to PR31500/PR31700 Connection using Two IT8368E
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 18
Epson Research and Development Vancouver Design Center
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping". The Generic MPU host interface control signals of the SED1354 are asynchronous with respect to the SED1354 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum SED1354 clock frequencies. The SED1354 also has internal clock dividers providing additional flexibility.
5.3 IT8368E Configuration
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E (or the first in a two-IT8368E implementation) must have both "Fix Attribute/IO" and "VGA" modes on. When both these modes are enabled, the MFIO pins provide control signals needed by the SED1354 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the SED1354. When accessing the SED1354 the associated card-side signals are disabled in order to avoid any conflicts.
Note
When a second IT8368E is used, it should not be set in VGA mode. For mapping details, refer to Section 5.4, `Memory Mapping and Aliasing" For further information on configuring the IT8368E, refer to the IT8368E PC Card/GPIO Buffer Chip Specification.
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 19
5.4 Memory Mapping and Aliasing
When the PR31500/PR31700 accesses the PC Card slots without the ITE IT8368E, its system memory is mapped as in Table 5-1:, "PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping".
Note
Bits CARD1IOEN and CARD2IOEN need to be set in the PR31500/PR31700 Memory Configuration Register 3. Table 5-1: PR31500/PR31700 to Unbuffered PC Card Slots System Address Mapping
TX3912 Address 0800 0000h 0C00 0000h 6400 0000h 6400 0000h Size 64M byte 64M byte 64M byte 64M byte Function (CARDnIOEN=0) Card 1 Attribute Card 2 Attribute Card 1 Memory Card 2 Memory Function (CARDnIOEN=1) Card 1 IO Card 2 IO
When the PR31500/PR31700 accesses the PC Card slots buffered through the ITE IT8368E, bits CARD1IOEN and CARD2IOEN are ignored and the attribute/IO space of the PR31500/PR31700 is divided into Attribute, IO and SED1354 access. Table 5-2:, "PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E" provides all the details of the Attribute/IO address re-allocation by the IT8368E. Table 5-2: PR31500/PR31700 to PC Card Slots Address Remapping using the IT8368E
IT8368E Uses PC Card Slot # Philips Address 0800 0000h 0900 0000h 1 0980 0000h 0A00 0000h 6400 0000h 0C00 0000h 0D00 0000h 2 0D80 0000h 0E00 0000h 6800 0000h Size 16M byte 8M byte 8M byte 32M byte 64M byte 16M byte 8M byte 8M byte 32M byte 64M byte Function Card 1 IO SED1354 registers, aliased 131,072 times at 64 byte intervals SED1354 display buffer, aliased 4 times at 2Mb intervals Card 1 Attribute Card 1 Memory Card 2 IO SED1354 registers, aliased 131,072 times at 64 byte intervals SED1354 display buffer, aliased 4 times at 2Mb intervals Card 2 Attribute Card 2 Memory
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 20
Epson Research and Development Vancouver Design Center
5.5 SED1354 Configuration
The SED1354 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Specification, document number X19A-A-002-xx. The partial table below only shows those configuration settings relevant to the IT8368E implementation. Table 5-3: SED1354 Configuration using the IT8368E
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 Little Endian WAIT# signal is active high Big Endian WAIT# signal is active low See "Host Bus Selection" table below See "Host Bus Selection" table below value on this pin at rising edge of RESET# is used to configure:(1/0) 1 8-bit host bus interface 0 16-bit host bus interface
= required configuration for connection using ITE IT8368E
Table 5-4: SED1354 Host Bus Selection using the IT8368E
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MCF5307, ISA bus interface) Reserved
= required configuration for connection using ITE IT8368E
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 21
6 Software
Test utilities and Windows(R) CE v2.0 display drivers are available for the SED1354. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1354CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The SED1354 test utilities and Windows CE v2.0 display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com.
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 22
Epson Research and Development Vancouver Design Center
7 References
7.1 Documents
* Philips Electronics, PR31500/PR31700 Preliminary Specifications. * Epson Research and Development, Inc., SED1354 Color Graphics LCD/CRT Controller Hardware Functional Specification, Document Number X19A-A-002-xx. * Epson Research and Development, Inc., SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. * Epson Research and Development, Inc., SED1354 Programming Notes and Examples, Document Number X19A-G-002-xx.
7.2 Document Sources
* Philips Electronics Website: http://www-us2.semiconductors.philips.com. * Epson Electronics America Website: http://www.eea.epson.com.
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 23
8 Technical Support
8.1 EPSON LCD/CRT Controllers (SED1354)
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346
8.2 Philips MIPS PR31500/PR31700 Processor
Philips Semiconductors Handheld Computing Group 4811 E. Arques Avenue M/S 42, P.O. Box 3409 Sunnyvale, CA 94088-3409 Tel: (408) 991-2313 http://www.philips.com
8.3 ITE IT8368E
Integrated Technology Express, Inc. Sales & Marketing Division 2710 Walsh Avenue Santa Clara, CA 95051, USA Tel: (408) 980-8168 Fax: (408) 980-9232 http://www.iteusa.com
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 X19A-G-005-07
Page 24
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-005-07
Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 99/03/10
SED1354 Color Graphics LCD/CRT Controller
Interfacing to the NEC VR4102TM Microprocessor
Document Number: X19A-G-007-06
Copyright (c) 1997, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interfacing to the NEC VR4102 . . 2.1 The NEC VR4102 System Bus . . 2.1.1 Overview . . . . . . . . . . 2.1.2 LCD Memory Access Cycles . . . . ....... ...... ........ ........ ... .. ... ... . . . . ...... ..... ....... ....... . . . . ....... ...... ........ ........ .8 .8 .8 .9
3
SED1354 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . 10 3.2 Generic MPU Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . 11 VR4102 to SED1354 Interface . . . 4.1 Hardware Description . . . . . 4.2 SED1354 Hardware Configuration 4.3 NEC VR4102TM Configuration . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . 12 12 13 14
4
5 6
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 EPSON LCD/CRT Controllers (SED1354) . . . . . . . . . . . . . . . . . . . 17 7.2 NEC Electronics Inc. (VR4102). . . . . . . . . . . . . . . . . . . . . . . . 17
7
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 3-1: Table 4-1: Table 4-2: Table 4-2: Generic MPU Host Bus Interface Pin Mapping Summary of Power-On/Reset Options . . . . . Host Bus Interface Selection . . . . . . . . . . NEC/SED1354 Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 13 13 14
List of Figures
Figure 2-1: NEC VR4102 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4-1: Typical Implementation of VR4102 to SED1354 Interface . . . . . . . . . . . . . . . . 12
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an interface between the SED1354 Color Graphics LCD/CRT Controller and the NEC VR4102TM Microprocessor (uPD30102). The NEC VR4102 Microprocessor is specifically designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 8
Epson Research and Development Vancouver Design Center
2 Interfacing to the NEC VR4102
2.1 The NEC VR4102 System Bus
The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE-based embedded consumer applications in mind, the VR4102 offers a highly integrated solution for portable systems. This section provides an overview of the operation of the CPU bus in order to establish interface requirements.
2.1.1 Overview
The NEC VR4102 is designed around the RISC architecture developed by MIPS. This microprocessor is based on the 66MHz VR4100 CPU core which supports 64-bit processing. The CPU communicates with the Bus Control Unit (BCU) using its internal SysAD bus. The BCU in turn communicates with external devices using its ADD and DAT buses which can be dynamically sized to 16 or 32-bit operation. The NEC VR4102 has direct support for an external LCD controller. Specific control signals are assigned for an external LCD controller providing an easy interface to the CPU. A 16M byte block of memory is assigned for the LCD controller and its own chip select and ready signals available. Word or byte accesses are controlled by the system high byte signal (SHB#).
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 9
2.1.2 LCD Memory Access Cycles
Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle. The high byte enable (SHB#) is driven low for 16-bit transfers and high for 8-bit transfers. The following figure illustrates typical NEC VR4102 memory read and write cycles to the LCD controller interface.
TCLK
ADD[25:0]
VALID
SHB#
LCDCS#
WR#,RD#
D[15:0] (write)
VALID
D[15:0] (read)
Hi-Z VALID
Hi-Z
LCDRDY
Figure 2-1: NEC VR4102 Read/Write Cycles
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 10
Epson Research and Development Vancouver Design Center
3 SED1354 Host Bus Interface
The SED1354 implements a 16-bit Generic MPU host bus interface which is used to interface to the VR4102 microprocessor. The Generic MPU host bus interface is the least processor-specific interface mode supported by the SED1354 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the SED1354 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic `1', meaning that the SED1354 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal. Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 11
3.2 Generic MPU Host Bus Interface Signals
The interface requires the following signals: * BUSCLK is a clock input which is required by the SED1354 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. * The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset. * M/R# (memory/register) may be considered an address line, allowing system address A21 to be connected to the M/R# line. * Chip Select (CS#) must be driven low whenever the SED1354 is accessed by the host CPU. * WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * RD# (RD0#) and RD/WR# (RD1#) are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * WAIT# is a signal output from the SED1354 that indicates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the SED1354 may occur asynchronously to the display update, it is possible that contention may occur in accessing the SED1354 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. * The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and should be tied low (connected to GND).
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 12
Epson Research and Development Vancouver Design Center
4 VR4102 to SED1354 Interface
4.1 Hardware Description
The NEC VR4102TM microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary. By using this interface only minimal external "glue" logic is necessary. The diagram below shows a typical implementation of the VR4102 to SED1354 interface.
NEC VR4102
Read/Write Decode Logic
A0
SED1354 WE0# WE1#
WR# SHB# A0 RD# RD1# LCDCS# LCDRDY A21
System RESET Pull-up
RD0#
CS# WAIT# M/R# RESET# AB[20:0] DB[15:0] BUSCLK
ADD[25:0] DAT[15:0] BUSCLK
Notes: The propagation delay of the Read/write Decode Logic shown above must be less than 10 nsec. When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of VR4102 to SED1354 Interface
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 13
4.2 SED1354 Hardware Configuration
The SED1354 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx. The tables below show only those configuration settings important to the PC Card host bus interface.
.
Table 4-1: Summary of Power-On/Reset Options
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 Little Endian Big Endian WAIT# is active high (1 = insert wait state) WAIT# is active low (0 = insert wait state) = configuration for NEC VR4102 interface. For host bus interface selection see Table 4-2, "Host Bus Interface Selection" value on this pin at rising edge of RESET# is used to configure: (1/0) 1 8-bit host bus interface 0 16-bit host bus interface
Table 4-2: Host Bus Interface Selection
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MPC821, ISA bus interface) Reserved
= configuration for NEC VR4102 interface.
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 14
Epson Research and Development Vancouver Design Center
4.3 NEC VR4102TM Configuration
The NEC VR4102TM provides the internal address decoding necessary to map to an external LCD controller. Physical address 0A00 0000h to 0AFF FFFFh (16M bytes) is reserved for an external LCD controller. The SED1354 supports up to 2M bytes of display buffer. The NEC VR4102TM address line A21 is used to select between the SED1354 display buffer and internal register set. The VR4102TM uses a read, write and system high-byte enable to interface to an external LCD controller. The SED1354 uses low and high byte read and write strobes and therefore minimal "glue" logic is necessary. Table 4-2: NEC/SED1354 Truth Table
NEC Signals SHB# 1 RD# 0 WR# 1 A0 0 Cycle 8-bit even address Read 8-bit odd address Read 16-bit Read 8-bit even address Write 8-bit odd address Write 16-bit Write SED1354 Signals RD0# = low RD1# = high RD0# = high RD1# - low RD0# = low RD1# - low WR0# = low WR1# = high WR0# = high WR1# = low WR0# = low WR1# = low
1
0
1
1
0
0
1
x
1
1
0
0
1
1
0
1
0
1
0
x
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 15
5 Software
Test utilities and Windows(R) CE v2.0 display drivers are available for the SED1354. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1354CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The SED1354 test utilities and Windows CE v2.0 display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com.
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 16
Epson Research and Development Vancouver Design Center
6 References
6.1 Documents
* NEC Electronics Inc., VR4102 Preliminary User's Manual, Document Number U12739EJ2V0UM00. * Epson Research and Development, Inc., SED1354 Hardware Functional Specification, Document Number X19A-A-002-xx. * Epson Research and Development, Inc., SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. * Epson Research and Development, Inc., SED1354 Programming Notes and Examples, Document Number X19A-G-002-xx.
6.2 Document Sources
* NEC Electronics Website: http://www.necel.com. * Epson Electronics America Website: http://www.eea.epson.com.
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 17
7 Technical Support
7.1 EPSON LCD/CRT Controllers (SED1354)
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
7.2 NEC Electronics Inc. (VR4102).
NEC Electronics Inc. (U.S.A.)Santa Clara California Tel: (800) 366-9782 Fax: (800) 729-9288 http://www.nec.com
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-007-06
Page 18
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-007-06
Interfacing to the NEC VR4102TM Microprocessor Issue Date: 99/03/10
SED1354 Color Graphics LCD/CRT Controller
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor
Document Number: X19A-G-011-06
Copyright (c) 1998, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interfacing to the MCF5307 . . . . . . . . . . . . 2.1 The MCF5307 System Bus . . . . . . . . . . 2.1.1 Overview . . . . . . . . . . . . . . . . . . . 2.1.2 Normal (Non-Burst) Bus Transactions . . . . 2.1.3 Burst Cycles . . . . . . . . . . . . . . . . . . 2.2 Chip-Select Module . . . . . . . . . . . . . ... .. ... ... ... .. . . . . . . ...... ..... ....... ....... ....... ..... . . . . . . ... .. ... ... ... .. .... .... ..... ..... ..... .... .8 .8 .8 .8 10 10
3
SED1354 Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . 11 3.2 Generic MPU Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . 12 MCF5307 To SED1354 Interface . . . 4.1 Hardware Connections . . . . . . 4.2 SED1354 Hardware Configuration . 4.3 Memory/Register Mapping . . . . 4.4 MCF5307 Chip Select Configuration . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . 13 13 14 15 15
4
5 6
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.1 EPSON LCD/CRT Controllers (SED1354) . . . . . . . . . . . . . . . . . . . 18 7.2 Motorola MCF5307 Processor . . . . . . . . . . . . . . . . . . . . . . . . 18
7
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 3-1: Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 11 Table 4-1: SED1354 Configuration Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4-2: SED1354 Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
Figure 2-1: MCF5307 Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2-2: MCF5307 Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4-1: Typical Implementation of MCF5307 to SED1354 Interface . . . . . . . . . . . . . . . 13
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an interface between the SED1354 Color Graphics LCD/CRT Controller and the Motorola MCF5307 "Coldfire" microprocessor. The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 8
Epson Research and Development Vancouver Design Center
2 Interfacing to the MCF5307
2.1 The MCF5307 System Bus
The MCF5200/5300 family of processors feature a high-speed synchronous system bus typical of modern microprocessors. This section provides an overview of the operation of the MCF5307 bus in order to establish interface requirements.
2.1.1 Overview
The MCF5307 microprocessor family uses a synchronous address and data bus, very similar in architecture to the MC68040 and MPC8xx. All outputs and inputs are timed with respect to a square-wave reference clock called BCLK0 (Master Clock). This clock runs at a software-selectable divisor rate from the machine cycle speed of the CPU core, typically 20 to 33 MHz. Both the address and the data bus are 32 bits in width. All IO accesses are memory-mapped; there is no separate IO space in the MCF5307 architecture. The bus can support two types of cycle, normal and burst. Burst memory cycles are used to fill on-chip cache memories, and for certain on-chip DMA operations. Normal cycles are used for all other data transfers.
2.1.2 Normal (Non-Burst) Bus Transactions
The bus master initiates a data transfer by placing the memory address on address lines A31 through A0 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: * SIZ[1:0] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32 bits in width. * R/W -- set high for read cycles and low for write cycles. * TT[1:0] (Transfer Type Signals) -- provides more detail on the type of transfer being attempted. * TIP (Transfer In Progress) -- asserts whenever a bus cycle is active. When the peripheral device being accessed has completed the bus transfer, it asserts TA (Transfer Acknowledge) for one clock cycle, completing the bus transaction. Once TA has been asserted, the MCF5307 will not start another bus cycle until TA has been de-asserted. The minimum length of a bus transaction is two bus clocks.
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 9
The following figure illustrates a typical memory read cycle on the MCF5307 system bus.
BCLK0 TS TA TIP A[31:0] R/W SIZ[1:0], TT[1:0] D[31:0] Transfer Start Wait States Transfer Complete Sampled when TA low Next Transfer Starts
Figure 2-1: MCF5307 Memory Read Cycle The following figure illustrates a typical memory read cycle on the MCF5307 system bus.
BCLK0 TS TA TIP A[31:0] R/W SIZ[1:0], TT[1:0] D[31:0] Transfer Start Valid Wait States Transfer Complete Next Transfer Starts
Figure 2-2: MCF5307 Memory Write Cycle
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 10
Epson Research and Development Vancouver Design Center
2.1.3 Burst Cycles
Burst cycles are very similar to normal cycles, except they occur as a series of four backto-back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output asserted continuously through the burst. Burst memory cycles are mainly intended to facilitate cache line fill from program or data memory. They are typically not used for transfers to/from IO peripheral devices such as the SED1354. The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them.
2.2 Chip-Select Module
In addition to generating eight independent chip-select outputs, the MCF5307 Chip Select Module can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible with most memory and x86-style peripherals. The MCF5307 bus controller also provides a Read/Write (R/W) signal which is compatible with most 68K peripherals. Chip selects 0 and 1 can be programmed independently to respond to any base address and block size. Chip select 0 can be active immediately after reset, and is typically used to control a boot ROM. Chip select 1 is typically used to control a large static or dynamic RAM block. Chip selects 2 through 7 have fixed block sizes of 2M bytes each. Each has a unique, fixed offset from a common, programmable starting address. These chip selects are well-suited to typical IO addressing requirements. Each chip select may be individually programmed for: * Port size (8/16/32-bit). * Number of wait states (0-15) or external acknowledge. * Address space type. * Burst or non-burst cycle support. * Write protect.
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 11
3 SED1354 Bus Interface
The SED1354 implements a 16-bit Generic MPU host bus interface which is used to interface to the MCF5307 microprocessor. The Generic MPU host bus interface is the least processor-specific interface mode supported by the SED1354. The Generic MPU host bus interface was chosen to implement this interface due to the simplicity of its timing and compatibility with the control signals available from the MCF5307's General-Purpose Chip Select Module. The Generic MPU host bus interface is selected by the SED1354 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic `1', meaning that the SED1354 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal. Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 12
Epson Research and Development Vancouver Design Center
3.2 Generic MPU Host Bus Interface Signals
The interface requires the following signals: * BUSCLK is a clock input which synchronizes transfers between the host CPU and the SED1354. It is separate from the pixel clock (CLKI) and is typically driven by the host CPU system clock. * The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset. * Chip Select (CS#) is driven by decoding the high-order address lines to select the proper IO or memory address space. * M/R# is driven high for memory accesses, or low for SED1354 register accesses. On CPUs which implement memory-mapped IO, this pin is typically tied to an address line; on CPUs with separate IO spaces, this pin is typically driven by control logic from the CPU. * WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the SED1354. * RD# and RD1# are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the SED1354. * WAIT# is a signal which is output from the SED1354 to the host CPU which indicates when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the SED1354 may occur asynchronously to the display update, it is possible that contention may occur in access to the 1354 internal registers and/or refresh memory. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. This signal is active low and needs to be inverted using MD5 since the MCF5307 wait state signal is active high. * The Bus Status (BS#) signal is unused in general purpose bus mode, and should be tied high (connected to IO VDD).
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 13
4 MCF5307 To SED1354 Interface
4.1 Hardware Connections
The interface between the SED1354 and the MCF5307 requires minimal glue logic. Since the SED1354 has a single chip select input for both display RAM and registers, a single external gate is required to produce a negative-OR function of the two MCF5307 chip selects. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle. BS# (bus start) is not used in this implementation and should be tied low (connected GND). The following diagram shows a typical implementation of the MCF5307 to SED1354 interface.
MCF5307 A21 A[20:0] D[31:16] CS4 CS5 74AC08 (or equiv.) CS# Vcc 470 TA WE1 WE0 OE WAIT# WE1# WE0# RD1# RD0# BCLK0
System RESET
SED1354 M/R# AB[20:0] DB[15:0]
BUSCLK RESET#
Note: When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of MCF5307 to SED1354 Interface
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping" .
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 14
Epson Research and Development Vancouver Design Center
4.2 SED1354 Hardware Configuration
The SED1354 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx. Table 4-1: SED1354 Configuration Settings
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 MD9 Little Endian Wait# signal is active high Configure SUSPEND# pin as GPO output = required settings for MCF5307 interface Big Endian Wait# signal is active low Configure SUSPEND# pin as Hardware Suspend Enable See "Host Bus Selection" table below See "Host Bus Selection" table below value on this pin at rising edge of RESET# is used to configure:(1/0) 1 8-bit host bus interface 0 16-bit host bus interface
Table 4-2: SED1354 Host Bus Selection
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MCF5307, ISA bus interface) Reserved
= required settings for MCF5307 interface.
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 15
4.3 Memory/Register Mapping
The SED1354 is a memory mapped device requiring a 2M byte address space for the display buffer and a few more locations for the internal registers. Chip selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes, however these chip selects would normally be needed to control system RAM and ROM. Two of the IO chip selects (CS2 through CS7) are required to address the entire address space of the SED1354, since these chip selects have a fixed 2M byte block size.
4.4 MCF5307 Chip Select Configuration
In the example interface, chip selects 4 and 5 are used to control the SED1354. CS4 selects a 2M byte address space for the SED1354 control registers, while CS5 selects the 2M byte display buffer. The CSBAR register should be set to the upper 8 bits of the desired base address. The following options should be selected in the chip select mask registers (CSMR4/5): * WP = 0 - disable write protect * AM = 0 - enable alternate bus master access to the SED1354 * C/I = 1 - disable CPU space access to the SED1354 * SC = 1 - disable Supervisor Code space access to the SED1354 * SD = 0 - enable Supervisor Data space access to the SED1354 * UC = 1 - disable User Code space access to the SED1354 * UD = 0 - enable User Data space access to the SED1354 * V = 1 - global enable ("Valid") for the chip select The following options should be selected in the chip select control registers (CSCR4/5): * WS0-3 = 0 - no internal wait state setting * AA = 0 - no automatic acknowledgment * PS (1:0) = 1:0 - memory port size is 16 bits * BEM = 0 - Byte enable/write enable active on writes only * BSTR = 0 - disable burst reads * BSTW = 0 - disable burst writes
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 16
Epson Research and Development Vancouver Design Center
5 Software
Test utilities and Windows(R) CE v2.0 display drivers are available for the SED1354. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1354CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The SED1354 test utilities and Windows CE v2.0 display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com.
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
Epson Research and Development Vancouver Design Center
Page 17
6 References
6.1 Documents
* Motorola Inc., MCF5307 ColdFire(R) Integrated Microprocessor User's Manual, Motorola Publication no. MCF5307UM/AD. * Epson Research and Development, Inc., SED1354 Hardware Functional Specification, Document Number X19A-A-002-xx. * Epson Research and Development, Inc., SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. * Epson Research and Development, Inc., SED1354 Programming Notes and Examples, Document Number X19A-G-002-xx.
6.2 Document Sources
* Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447. * Motorola Website: http://www.mot.com. * Epson Electronics America Website: www.eea.epson.com.
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 X19A-G-011-06
Page 18
Epson Research and Development Vancouver Design Center
7 Technical Support
7.1 EPSON LCD/CRT Controllers (SED1354)
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
7.2 Motorola MCF5307 Processor
* Motorola Design Line, (800) 521-6274. * Local Motorola sales office or authorized distributor.
SED1354 X19A-G-011-06
Interfacing to the Motorola MCF5307 "Coldfire" Microprocessor Issue Date: 99/12/23
SED1354 Color Graphics LCD / CRT Controller
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor
Document Number: X19A-G-013-01
Copyright (c) 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All Trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interfacing to the MC68328 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 The 68328 System Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Chip-Select Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SED1354 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . 9 3.2 Generic MPU Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . 10 MC68328 To SED1354 Interface . . . 4.1 Hardware Description . . . . . . 4.2 SED1354 Hardware Configuration . 4.3 MC68328 Chip Select Configuration . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . 11 11 13 14
3
4
5 6
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 EPSON LCD/CRT Controllers (SED1354) . . . . . . . . . . . . . . . . . . . 17 7.2 Motorola MC68328 Processor . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 3-1: Table 4-1: Table 4-2: Table 4-3: Generic MPU Host Bus Interface Pin Mapping Summary of Power-On/Reset Options . . . . SED1354 Host Bus Selection . . . . . . . . . Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 13 13 14
List of Figures
Figure 4-1: Block Diagram of MC68328 to SED1354 Interface - MC68000 Bus 1 Interface Mode . 11 Figure 4-2: Block Diagram of MC68328 to SED1354 Interface - Generic Interface Mode . . . . . . 12
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware required to implement an interface between the SED1354 Color Graphics LCD/CRT Controller and the Motorola MC68328 `Dragonball' Microprocessor. By implementing a dedicated display refresh memory, the SED1354 can reduce system power consumption, improve image quality, and increase system performance as compared to the Dragonball's on-chip LCD controller. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America website at http://www.eea.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 8
Epson Research and Development Vancouver Design Center
2 Interfacing to the MC68328
2.1 The 68328 System Bus
The 68328 is an integrated controller for handheld products, based upon the MC68EC000 microprocessor core. It implements a 16-bit data bus and a 32-bit address bus. The bus interface consists of all the standard MC68000 bus interface signals, plus some new signals intended to simplify the task of interfacing to typical memory and peripheral devices. The 68000 bus control signals are well documented in Motorola's user manuals, and will not be described here (see reference 1 for details). A brief summary of the new signals appears below: * Output Enable (OE) is asserted when a read cycle is in process; it is intended to connect to the output enable control of a typical static RAM, EPROM, or Flash EPROM device. * Upper Write Enable and Lower Write Enable (UWE/LWE) are asserted during memory write cycles for the upper and lower bytes of the 16-bit data bus; they may be directly connected to the write enable inputs of a typical memory device. The SED1354 implements the MC68000 bus interface using its MC68000 Bus 1 mode, so this mode may be used to connect the 68328 directly to the SED1354 with no glue logic. However, several of the 68000 bus control signals are multiplexed with I/O and interrupt signals on the 68328, and in many applications it may be desirable to make these pins available for these alternate functions. This requirement may be accommodated through use of the Generic Bus interface mode on the SED1354.
2.2 Chip-Select Module
The 68328 can generate up to 16 chip select outputs, organized into four groups "A" through "D". Each chip select group has a common base address register and address mask register, to set the base address and block size of the entire group. In addition, each chip select within a group has its own address compare and address mask register, to activate the chip select for a subset of the group's address block. Finally, each chip select may be individually programmed to control an 8 or 16-bit device, and each may be individually programmed to generate from 0 through 6 wait states internally, or allow the memory or peripheral device to terminate the cycle externally through use of the standard MC68000 DTACK signal. Groups A and B can have a minimum block size of 64K bytes, so these are typically used to control memory devices. Chip select A0 is active immediately after reset, so it is typically used to control a boot EPROM device. Groups C and D have a minimum block size of 4K bytes, so they are well-suited to controlling peripheral devices. Chip select D3 is associated with the 68328 on-chip PCMCIA control logic.
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 9
3 SED1354 Host Bus Interface
This section is summary of the bus interface modes available on the SED1354, and offers some detail on the Generic MPU host bus interface used to implement the interface to the MC68328. The Generic MPU host bus interface is selected by the SED1354 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic `1', meaning that the SED1354 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal. Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 10
Epson Research and Development Vancouver Design Center
3.2 Generic MPU Host Bus Interface Signals
The interface requires the following signals: * BUSCLK is a clock input which is required by the SED1354 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. * The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset. * M/R# (memory/register) may be considered an address line, allowing system address A21 to be connected to the M/R# line. * Chip Select (CS#) must be driven low whenever the SED1354 is accessed by the host CPU. * WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * RD# (RD0#) and RD/WR# (RD1#) are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * WAIT# is a signal output from the SED1354 that indicates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the SED1354 may occur asynchronously to the display update, it is possible that contention may occur in accessing the SED1354 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. * The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and should be tied low (connected to GND).
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 11
4 MC68328 To SED1354 Interface
4.1 Hardware Description
As mentioned earlier in this application note, the MC68328 multiplexes dual functions on some of its bus control pins, specifically UDS, LDS, and DTACK. If all of these pins are available for use as bus control pins, then the SED1354 interface is a straightforward implementation of the MC68000 Bus 1 interface mode as described in the SED1354 Hardware Functional Specification, document number X19A-A-002-xx. Following are the electrical connections required for this interface.
MC68328 A21 A[20:1] D[15:0] CSB3 Vcc 470 DTACK AS UDS LDS R/W Vcc CLK0
System RESET
SED1354 M/R# AB[20:1] SD[15:0] CS#
WAIT# BS# WE1# AB0 RD1# RD0# BUSCLK RESET#
Note: When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-1: Block Diagram of MC68328 to SED1354 Interface - MC68000 Bus 1 Interface Mode
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 12
Epson Research and Development Vancouver Design Center
If UDS and/or LDS are required for their alternate I/O functions, then the 68328 to SED1354 interface may be realized using the SED1354 Generic bus interface mode. The electrical connections required for this interface are shown below. Note that in either case, the DTACK signal must be made available for the SED1354, since it inserts a variable number of wait states depending upon CPU/LCD synchronization and the LCD panel display mode being used. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle.
MC68328 A21 A[20:1] D[15:0] CSB3 Vcc 470 DTACK
SED1354 M/R# AB[20:1] SD[15:0] CS#
WAIT#
UWE LWE OE
WE1# WE0# RD1# RD0#
CLK0
System RESET
BUSCLK RESET#
Note: When connecting the SED1354/55 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354/55 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-2: Block Diagram of MC68328 to SED1354 Interface - Generic Interface Mode The SED1354 requires a 2M byte address space for the display buffer, plus a few more locations to access its internal registers. To accommodate this relatively large block size, it is preferable to use one of the chip selects from groups A or B, but this is not required. Virtually any chip select other than CSA0 or CSD3 would be suitable for the SED1354 interface.
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 13
4.2 SED1354 Hardware Configuration
The SED1354 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. Table 4-2 shows the settings used for the SED1354 in these interfaces. MD1, MD2, and MD3 should be set to select either MC68000 Bus 1 mode or Generic bus mode as desired. The other settings are identical for either bus mode. Table 4-1: Summary of Power-On/Reset Options
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 Little Endian Wait# signal is active high See "Memory Configuration" table below Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as GPIO4-11 Configure SUSPEND# pin as GPO output Active low (On) LCDPWR / GPO polarity Reserved Reserved Reserved Reserved Reserved = required settings for MC68328 support. Big Endian Wait# signal is active low See "Memory Configuration" table below Configure DACRD#, BLANK#, DACP0, DACWR#, DACRS0, DACRS1, HRTC, VRTC as DAC / CRT outputs Configure SUSPEND# pin as Hardware Suspend Enable Active high (On) LCDPWR / GPO polarity See "Host Bus Selection" table below See "Host Bus Selection" table below value on this pin at rising edge of RESET# is used to configure:(1/0) 1 8-bit host bus interface 0 16-bit host bus interface
Table 4-2: SED1354 Host Bus Selection
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Option 1 2 3 4 5 Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MC68328, ISA bus interface) Reserved
= required settings for MC68328 support.
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 14
Epson Research and Development Vancouver Design Center
Table 4-3: Memory Configuration
MD7 0 0 1 1 MD6 0 1 0 1 Option 1 2 3 4 Memory Selection Symmetrical 256K x 16 DRAM Symmetrical 1M x 16 DRAM Asymmetrical 256K x 16 DRAM Asymmetrical 1M x 16 DRAM
4.3 MC68328 Chip Select Configuration
In the example interface, chip select CSB3 is used to control the SED1354. A 4M byte address space is used. The SED1354 control registers are mapped into the bottom half of this address block, while the display buffer is mapped into the top half. The chip select should have its RO (Read Only) bit set to 0, and the WAIT field (Wait states) should be set to 111 to allow the SED1354 to terminate bus cycles externally.
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 15
5 Software
Test utilities and Windows(R) CE v2.0 display drivers are available for the SED1354. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1354CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The SED1354 test utilities and Windows CE v2.0 display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com.
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 16
Epson Research and Development Vancouver Design Center
6 References
6.1 Documents
* Motorola Inc., MC68328 DragonBall(R) Integrated Microprocessor User's Manual; Motorola Publication no. MC68328UM/AD. * Epson Research and Development, Inc., SED1354 Hardware Functional Specification, Document Number X19A-A-002-xx. * Epson Research and Development, Inc., SED1354 Programming Notes and Examples, Document Number X19A-G-002-xx. * Epson Research and Development, Inc., SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx.
6.2 Document Sources
* Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447. * Epson Electronics America Website: http://www.eea.epson.com.
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
Epson Research and Development Vancouver Design Center
Page 17
7 Technical Support
7.1 EPSON LCD/CRT Controllers (SED1354)
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
7.2 Motorola MC68328 Processor
* Motorola Design Line, (800) 521-6274. * Local Motorola sales office or authorized distributor.
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 X19A-G-013-01
Page 18
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-013-01
Interfacing to the Motorola MC68328 "Dragonball" Microprocessor Issue Date: 99/04/19
SED1354 Color Graphics LCD/CRT Controller
Interfacing to the Motorola MPC821 Microprocessor
Document Number: X19A-G-010-04
Copyright (c) 1998, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interfacing to the MPC821 . . . . . . . . . . . . . . . . 2.1 The MPC8xx System Bus . . . . . . . . . . . . . 2.2 MPC821 Bus Overview . . . . . . . . . . . . . 2.2.1 Normal (Non-Burst) Bus Transactions . . . . . . . 2.3 Memory Controller Module . . . . . . . . . . . . 2.3.1 General-Purpose Chip Select Module (GPCM) . . . 2.3.2 User-Programmable Machine (UPM) . . . . . . . . . . . . . . . ...... ..... ..... ....... ..... ....... ....... . . . . . . . ... .. .. ... .. ... ... .... .... .... ..... .... ..... ..... .8 .8 .8 .9 11 11 12
3
SED1354 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . 13 3.2 Generic MPU Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . 14 MPC821 to SED1354 Interface . . . 4.1 Hardware Description . . . . . 4.2 Hardware Connections . . . . . 4.3 SED1354 Hardware Configuration 4.4 Register/Memory Mapping . . . 4.5 MPC821 Chip Select Configuration 4.6 Test Software . . . . . . . . 4.6.1 Source Code . . . . . . . . . . . . . . . . . ....... ...... ...... ...... ...... ...... ...... ........ ... .. .. .. .. .. .. ... . . . . . . . . ...... ..... ..... ..... ..... ..... ..... ....... . . . . . . . . ....... ...... ...... ...... ...... ...... ...... ........ 15 15 16 18 19 19 20 20
4
5 6
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 EPSON LCD/CRT Controllers (SED1354) . . . . . . . . . . . . . . . . . . . 24 7.2 Motorola MPC821 Processor . . . . . . . . . . . . . . . . . . . . . . . . 24
7
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 3-1: Table 4-1: Table 4-2: Table 4-2: Generic MPU Host Bus Interface Pin Mapping . . . List of Connections from MPC821ADS to SED1354 Summary of Power-On/Reset Options . . . . . . . Host Bus Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 16 18 18
List of Figures
Figure 2-1: Power PC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2-2: Power PC Memory Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 4-1: Typical Implementation of MPC821 to SED1354 Interface . . . . . . . . . . . . . . . . 15
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an interface between the SED1354 Color Graphics LCD/CRT Controller and the Motorola MPC821 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 8
Epson Research and Development Vancouver Design Center
2 Interfacing to the MPC821
2.1 The MPC8xx System Bus
The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern RISC microprocessors. This section provides an overview of the operation of the CPU bus in order to establish interface requirements.
2.2 MPC821 Bus Overview
The MPC8xx microprocessor family uses a synchronous address and data bus. All IO is synchronous to a square-wave reference clock called MCLK (Master Clock). This clock runs at the machine cycle speed of the CPU core (typically 25 to 50 MHz). Most outputs from the processor change state on the rising edge of this clock. Similarly, most inputs to the processor are sampled on the rising edge.
Note
The external bus can run at one-half the CPU core speed using the clock control register. This is typically used when the CPU core is operated above 50 MHz. The MPC821 can generate up to eight independent chip select outputs, each of which may be controlled by one of two types of timing generators: the General Purpose Chip Select Module (GPCM) or the User-Programmable Machine (UPM). Examples are given using the GPCM. It should be noted that all Power PC microprocessors, including the MPC8xx family, use bit notation opposite from the convention used by most other microprocessor systems. Bit numbering for the MPC8xx always starts with zero as the most significant bit, and increments in value to the least-significant bit. For example, the most significant bits of the address bus and data bus are A0 and D0, while the least significant bits are A31 and D31. The MPC8xx uses both a 32-bit address and data bus. A parity bit is supported for each of the four byte lanes on the data bus. Parity checking is done when data is read from external memory or peripherals, and generated by the MPC8xx bus controller on write cycles. All IO accesses are memory-mapped meaning there is no separate IO space in the Power PC architecture. Support is provided for both on-chip (DMA controllers) and off-chip (other processors and peripheral controllers) bus masters. For further information on this topic, refer to Section 6, "References" on page 23. The bus can support both normal and burst cycles. Burst memory cycles are used to fill on-chip cache memory, and for certain on-chip DMA operations. Normal cycles are used for all other data transfers.
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 9
2.2.1 Normal (Non-Burst) Bus Transactions
A data transfer is initiated by the bus master by placing the memory address on address lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: * TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit. * RD/WR -- set high for read cycles and low for write cycles. * AT[0:3] (Address Type Signals) -- provides more detail on the type of transfer being attempted. When the peripheral device being accessed has completed the bus transfer, it asserts TA (Transfer Acknowledge) for one clock cycle to complete the bus transaction. Once TA has been asserted, the MPC821 will not start another bus cycle until TA has been de-asserted. The minimum length of a bus transaction is two bus clocks. The following figure illustrates a typical memory read cycle on the Power PC system bus.
SYSCLK TS TA A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Transfer Start Wait States Transfer Complete Sampled when TA low Next Transfer Starts
Figure 2-1: Power PC Memory Read Cycle
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 10
Epson Research and Development Vancouver Design Center
The following figure illustrates a typical memory write cycle on the Power PC system bus.
SYSCLK TS TA A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Transfer Start Valid Wait States Transfer Complete Next Transfer Starts
Figure 2-2: Power PC Memory Write Cycle If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is aborted. For example, a peripheral device may assert TEA if a parity error is detected, or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time-out period. For 32-bit transfers, all data lines (D[0:31]) are used and the two low-order address lines A30 and A31 are ignored. For 16-bit transfers, data lines D0 through D15 are used and address line A30 is ignored. For 8-bit transfers, data lines D0 through D7 are used and all address lines (A[0:31]) are used.
Note
This assumes that the Power PC core is operating in big endian mode (typically the case for embedded systems).
2.1.3
Burst Cycles
Burst memory cycles are used to fill on-chip cache memory and to carry out certain on-chip DMA operations. They are very similar to normal bus cycles with the following exceptions: * Always 32-bit. * Always attempt to transfer four 32-bit words sequentially. * Always address longword-aligned memory (i.e. A30 and A31 are always 0:0). * Do not increment address bits A28 and A29 between successive transfers; the addressed device must increment these address bits internally. If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI) simultaneously with TA, and the processor will revert to normal bus cycles for the remaining data transfers.
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 11
Burst cycles are mainly intended to facilitate cache line fills from program or data memory. They are normally not used for transfers to/from IO peripheral devices such as the SED1354, therefore the interfaces described in this document do not attempt to support burst cycles. However, the example interfaces include circuitry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the SED1354 address space.
2.3 Memory Controller Module
2.3.1 General-Purpose Chip Select Module (GPCM)
The General-Purpose Chip Select Module (GPCM) is used to control memory and peripheral devices which do not require special timing or address multiplexing. In addition to the chip select output, it can generate active-low Output Enable (OE) and Write Enable (WE) signals compatible with most memory and x86-style peripherals. The MPC821 bus controller also provides a Read/Write (RD/WR) signal which is compatible with most 68K peripherals. The GPCM is controlled by the values programmed into the Base Register (BR) and Option Register (OR) of the respective chip select. The Option Register sets the base address, the block size of the chip select, and controls the following timing parameters: * The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid, by 0, 1/4, or 1/2 clock cycle. * The CSNT bit causes chip select and WE to be negated 1/2 clock cycle earlier than normal. * The TRLX (relaxed timing) bit will insert an additional one clock delay between assertion of the address bus and chip select. This accommodates memory and peripherals with long setup times. * The EHTR (Extended hold time) bit will insert an additional 1-clock delay on the first access to a chip select. * Up to 15 wait states may be inserted, or the peripheral can terminate the bus cycle itself by asserting TA (Transfer Acknowledge). * Any chip select may be programmed to assert BI (Burst Inhibit) automatically when its memory space is addressed by the processor core.
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 12
Epson Research and Development Vancouver Design Center
2.3.2 User-Programmable Machine (UPM)
The UPM is typically used to control memory types, such as Dynamic RAMs, which have complex control or address multiplexing requirements. The UPM is a general purpose RAM-based pattern generator which can control address multiplexing, wait state generation, and five general-purpose output lines on the MPC821. Up to 64 pattern locations are available, each 32 bits wide. Separate patterns may be programmed for normal accesses, burst accesses, refresh (timer) events, and exception conditions. This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821. In this application note, the GPCM is used instead of the UPM, since the GPCM has enough flexibility to accommodate the SED1354 and it is desirable to leave the UPM free to handle other interfacing duties, such as EDO DRAM.
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 13
3 SED1354 Host Bus Interface
The SED1354 implements a 16-bit Generic MPU host bus interface which is used to interface to the MPC821 processor. The Generic MPU host bus interface is the least processor-specific interface mode supported by the SED1354. Although the Power PC bus is similar in many respects to the M68K bus, the Generic MPU host bus interface was chosen for this interface due to the simplicity of its timing and compatibility with the control signals available from the MPC821 General-Purpose Chip Select Module. The Generic MPU host bus interface is selected by the SED1354 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic `1', meaning that the SED1354 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal. Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 14
Epson Research and Development Vancouver Design Center
3.2 Generic MPU Host Bus Interface Signals
The interface requires the following signals: * BUSCLK is a clock input which is required by the SED1354 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. * The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset. * M/R# (memory/register) may be considered an address line, allowing system address A21 to be connected to the M/R# line. * Chip Select (CS#) must be driven low whenever the SED1354 is accessed by the host CPU. * WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the SED1354. * RD# (RD0#) and RD/WR# (RD1#) are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the SED1354. * WAIT# is a signal output from the SED1354 that indicates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the SED1354 may occur asynchronously to the display update, it is possible that contention may occur in accessing the SED1354 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. This signal is active low and must be inverted using MD5 since the MPC821 wait state signal is active high. * The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and should be tied low (connected to GND).
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 15
4 MPC821 to SED1354 Interface
4.1 Hardware Description
The interface between the SED1354 and the MPC821 requires no glue logic. All lines are directly connected. A single resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the bus cycle. BS# (bus start) is not used in this implementation and should be tied low (connected to GND). The following diagram shows a typical implementation of the MPC821 to SED1354 interface.
MPC821 A10 A[11:31] D[0:15] CS4 Vcc 470 TA WE0 WE1 OE WAIT# WE1# WE0# RD1# RD0# SYSCLK
System RESET
SED1354 M/R# AB[20:0] DB[15:0] CS#
BUSCLK RESET#
Note: When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of MPC821 to SED1354 Interface
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping" .
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 16
Epson Research and Development Vancouver Design Center
4.2 Hardware Connections
The following table details the connections between the pins and signals of the MPC821 and the SED1354. Table 4-1: List of Connections from MPC821ADS to SED1354
MPC821 Signal Name Vcc A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 MPC821ADS Connector and Pin Name P6-A1, P6-B1 P6-C23 P6-A22 P6-B22 P6-C21 P6-C20 P6-D20 P6-B24 P6-C24 P6-D23 P6-D22 P6-D19 P6-A19 P6-D28 P6-A28 P6-C27 P6-A26 P6-C26 P6-A25 P6-D26 P6-B25 P6-B19 P6-D17 P12-A9 P12-C9 P12-D9 P12-A8 P12-B8 P12-D8 P12-B7 P12-C7 P12-A15 P12-C15 P12-D15 P12-A14 SED1354 Signal Name Vcc M/R# AB20 AB19 AB18 AB17 AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 17
Table 4-1: List of Connections from MPC821ADS to SED1354 (Continued)
MPC821 Signal Name D12 D13 D14 D15 SRESET SYSCLK CS4 TA WE0 WE1 OE MPC821ADS Connector and Pin Name P12-B14 P12-D14 P12-B13 P12-C13 P9-D15 P9-C2 P6-D13 P6-B6 P6-B15 P6-A14 P6-B16 P12-A1, P12-B1, P12-A2, P12-B2, P12-A3, P12-B3, P12-A4, P12-B4, P12-A5, P12-B5, P12-A6, P12-B6, P12-A7 SED1354 Signal Name DB3 DB2 DB1 DB0 RESET# BUSCLK CS# WAIT# WE1# WE0# RD1#, RD0#
Gnd
Vss
Note
Note that the bit numbering of the Power PC bus signals is reversed from convention, e.g.: the most significant address bit is A0, the next is A1, A2, etc.
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 18
Epson Research and Development Vancouver Design Center
4.3 SED1354 Hardware Configuration
The SED1354 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx. The tables below show only those configuration settings important to the MPC821 interface.
.
Table 4-2: Summary of Power-On/Reset Options
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 MD9 Little Endian Wait# signal is active high Reserved = configuration for MPC821 interface. Big Endian Wait# signal is active low Configure SUSPEND# pin as Hardware Suspend Enable For host bus interface selection see Table 4-2, "Host Bus Interface Selection" value on this pin at rising edge of RESET# is used to configure: (1/0) 1 8-bit host bus interface 0 16-bit host bus interface
Table 4-2: Host Bus Interface Selection
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MPC821, ISA bus interface) Reserved
= configuration for MPC821 interface.
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 19
4.4 Register/Memory Mapping
The SED1354 is a memory mapped device. The DRAM on the MPC821 ADS board extends from address 0h through 3F FFFFh, so the SED1354 must be addressed starting at 40 0000h. A total of 4M bytes of address space is used, where the lower 2M bytes (from 40 0000h through 5F FFFFh) is reserved for the SED1354 on-chip registers and the upper 2M bytes (from 60 0000h through 7F FFFFh) is used for the SED1354 display buffer.
4.5 MPC821 Chip Select Configuration
Chip select 4 is used to control the SED1354. The following options are selected in the base address register (BR4): * BA[0:16] = 0000 0000 0100 0000 0 - set starting address of SED1354 to 40 0000h. * AT[0:2] = 0 - ignore address type bits. * PS[0:1] = 1:0 - memory port size is 16-bit. * PARE = 0 - disable parity checking. * WP = 0 - disable write protect. * MS[0:1] = 0:0 - select General Purpose Chip Select module to control this chip select. * V = 1 - set valid bit to enable chip select. The following options were selected in the option register (OR4): * AM[0:16] = 1111 1111 1100 0000 0 - mask all but upper 10 address bits; SED1354 consumes 4M byte of address space. * ATM[0:2] = 0 - ignore address type bits. * CSNT = 0 - normal CS/WE negation. * ACS[0:1] = 1:1 - delay CS assertion by 1/2 clock cycle from address lines. * BI = 1 - assert Burst Inhibit. * SCY[0:3]= 0 - wait state selection; this field is ignored since external transfer acknowledge is used; see SETA below. * SETA = 1 - the SED1354 generates an external transfer acknowledge using the WAIT# line. * TRLX = 0 - normal timing. * EHTR = 0 - normal timing.
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 20
Epson Research and Development Vancouver Design Center
4.6 Test Software
The test software used to exercise this interface is very simple. It carries out the following functions: 1. Configures chip select 4 on the MPC821 to map the SED1354 to an unused 4M byte block of address space. 2. Loads the appropriate values into the option register for CS4. 3. Enables the SED1354 host bus interface by writing the value 0 to REG[1Bh]. At that point the software runs in a tight loop which reads the SED1354 Revision Code Register REG[00h]. This allows monitoring of the bus timing on a logic analyzer. This source code for the following test routine was entered into the memory of the MPC821ADS using the line-by-line assembler in MPC8BUG (the debugger provided with the ADS board). It was run on the ADS and a logic analyzer was used to verify operation of the interface hardware.
4.6.1 Source Code
BR4 OR4 MemStart DisableReg RevCodeReg Start equ equ equ equ equ mfspr andis. andis. oris ori stw andis. oris ori stw andis. oris stb lbz b $120 $124 $40 $1b 0 r1,IMMR r1,r1,$ffff r2,r0,0 r2,r2,MemStart r2,r2,$0801 r2,BR4(r1) r2,r0,0 r2,r2,$ffc0 r2,r2,$0708 ; ; ; ; ; CS4 base register CS4 option register upper word of SED1354 start address address of SED1354 Disable Register address of Revision Code Register get base address of internal registers clear lower 16 bits to 0 clear r2 write base address port size 16 bits; select GPCM; enable write value to base register clear r2 address mask - use upper 10 bits normal CS negation; delay CS 1/2 clock; inhibit burst write to option register clear r1 point r1 to start of SED1354 mem space write 0 to disable register read revision code into r1 branch forever
Loop
; ; ; ; ; ; ; ; ; ; r2,OR4(r1) ; r1,r0,0 ; r1,r1,MemStart ; r1,DisableReg(r1) ; r0,RevCodeReg(r1) ; Loop ;
end
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 21
Note
MPC8BUG does not support comments or symbolic equates; these have been added for clarity.
Note
It is important to note that when the MPC821 comes out of reset, its on-chip caches and MMU are disabled. If the data cache is enabled, the MMU must be setup so the SED1354 memory block is tagged as non-cacheable. This ensures that accesses to the SED1354 will occur in proper order, and the MPC821 will not attempt to cache any data read from or written to the SED1354 or its display buffer.
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 22
Epson Research and Development Vancouver Design Center
5 Software
Test utilities and Windows(R) CE v2.0 display drivers are available for the SED1354. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1354CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The SED1354 test utilities and Windows CE v2.0 display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com.
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 23
6 References
6.1 Documents
* Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User's Manual, Motorola Publication no. MPC821UM/AD. * Epson Research and Development, Inc., SED1354 Color Graphics LCD/CRT Controller Hardware Functional Specification, Document Number X19A-A-002-xx. * Epson Research and Development, Inc., SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. * Epson Research and Development, Inc., SED1354 Programming Notes and Examples, Document Number X19A-G-002-xx.
6.2 Document Sources
* Motorola Inc.: Motorola Literature Distribution Center, (800) 441-2447. * Motorola Website: http://www.mot.com. * Epson Electronics America Website: http://www.eea.epson.com.
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 X19A-G-010-04
Page 24
Epson Research and Development Vancouver Design Center
7 Technical Support
7.1 EPSON LCD/CRT Controllers (SED1354)
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
7.2 Motorola MPC821 Processor
* Motorola Design Line, (800) 521-6274. * Local Motorola sales office or authorized distributor.
SED1354 X19A-G-010-04
Interfacing to the Motorola MPC821 Microprocessor Issue Date: 99/03/10
SED1354 Color Graphics LCD/CRT Controller
Interfacing to the PC Card Bus
Document Number: X19A-G-009-04
Copyright (c) 1998, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interfacing to the PC Card Bus 2.1 The PC Card System Bus . . 2.1.1 PC Card Overview . . 2.1.2 Memory Access Cycles ... ... .... .... ... .. ... ... .... .... ..... ..... ... .. ... ... . . . . ...... ..... ....... ....... . . . . ... .. ... ... .... .... ..... ..... .8 .8 .8 .8
3
SED1354 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . 10 3.2 Generic MPU Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . 11 PC Card to SED1354 Interface . . . 4.1 Hardware Description . . . . . 4.2 SED1354 Hardware Configuration 4.3 PAL Equations . . . . . . . . 4.4 Register/Memory Mapping . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . ... .. .. .. .. . . . . . . . . . . . . . . . 12 12 13 14 14
4
5 6
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 EPSON LCD/CRT Controllers (SED1354) . . . . . . . . . . . . . . . . . . . 17 7.2 PC Card Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 3-1: Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . 10 Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4-2: Host Bus Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures
Figure 2-1: PC Card Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2-2: PC Card Write Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4-1: Typical Implementation of PC Card to SED1354 Interface . . . . . . . . . . . . . . . . 12
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an interface between the SED1354 Color Graphics LCD/CRT Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 8
Epson Research and Development Vancouver Design Center
2 Interfacing to the PC Card Bus
2.1 The PC Card System Bus
PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness. This section is an overview of the operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1 Standard (or later).
2.1.1 PC Card Overview
The 16-bit PC Card provides a 26-bit address bus and additional control lines which allow access to three 64M byte address ranges. These ranges are used for common memory space, IO space, and attribute memory space. Common memory may be accessed by a host system for memory read and write operations. Attribute memory is used for defining card specific information such as configuration registers, card capabilities, and card use. IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture, which address peripherals independently from memory space. Bit notation follows the convention used by most micro-processors, the high bit is the most significant. Therefore, signals A25 and D15 are the most significant bits for the address and data bus respectively. Support is provided for on-chip DMA controllers. To find further information on these topics, refer to Section 6,"References" on page 16. PC Card bus signals are asynchronous to the host CPU bus signals. Bus cycles are started with the assertion of either the CE1# and/or the CE2# card enable signals. The cycle ends once these signals are de-asserted. Bus cycles can be lengthened using the WAIT# signal.
Note
The PCMCIA 2.0/JEIDA 4.1 (and later) PC Card Standard support the two signals WAIT# and RESET which are not supported in earlier versions of the standard. The WAIT# signal allows for asynchronous data transfers for memory, attribute, and IO access cycles. The RESET signal allows resetting of the card configuration by the reset line of the host CPU.
2.1.2 Memory Access Cycles
A data transfer is initiated when the memory address is placed on the PC Card bus and one, or both, of the card enable signals (CE1# and CE2#) are driven low. REG# must be kept inactive. If only CE1# is driven low, 8-bit data transfers are enabled and A0 specifies whether the even or odd data byte appears on data bus lines D[7:0]. If both CE1# and CE2# are driven low, a 16-bit word transfer takes place. If only CE2# is driven low, an odd byte transfer occurs on data lines D[15:8].
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 9
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by driving OE# high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT# low for the time needed to complete the cycle. The figure below illustrates a typical memory read cycle on the PC Card bus.
A[25:0] REG#
ADDRESS VALID
CE1# CE2#
OE#
WAIT#
D[15:0]
Hi-Z DATA VALID
Hi-Z
Transfer Start
Transfer Complete
Figure 2-1: PC Card Read Cycle The figure below illustrates a typical memory write cycle on the PC Card bus.
A[25:0] REG#
ADDRESS VALID
CE1# CE2#
OE#
WE#
WAIT#
D[15:0]
Hi-Z
DATA VALID
Hi-Z
Transfer Start
Transfer Complete
Figure 2-2: PC Card Write Cycle
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 10
Epson Research and Development Vancouver Design Center
3 SED1354 Host Bus Interface
The SED1354 implements a 16-bit Generic MPU host bus interface which is used to interface to the PC Card bus. The Generic MPU host bus interface is the least processorspecific interface mode supported by the SED1354 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the SED1354 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic `1', meaning that the SED1354 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal. Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 11
3.2 Generic MPU Host Bus Interface Signals
The Generic MPU host bus interface requires the following signals: * BUSCLK is a clock input which is required by the SED1354 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. * The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset. * M/R# (memory/register) may be considered an address line, allowing system address A21 to be connected to the M/R# line. * Chip Select (CS#) must be driven low whenever the SED1354 is accessed by the host CPU. * WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * RD# (RD0#) and RD/WR# (RD1#) are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * WAIT# is a signal output from the SED1354 that indicates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the SED1354 may occur asynchronously to the display update, it is possible that contention may occur in accessing the SED1354 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. * The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and should be tied low (connected to GND).
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 12
Epson Research and Development Vancouver Design Center
4 PC Card to SED1354 Interface
4.1 Hardware Description
The SED1354 is interfaced to the PC Card bus with a minimal amount of glue logic. A PAL is used to decode the read and write signals of the PC Card bus which generate RD#, RD/WR#, WE0#, WE1#, and CS# for the SED1354. The PAL also inverts the reset signal of the PC card since it is active high and the SED1354 uses an active low reset. PAL equations for this implementation are listed in Section 4.3,"PAL Equations" on page 14. In this implementation, the address inputs (AB[20:0]) and data bus (DB[15:0] connect directly to the CPU address (A[20:0]) and data bus (D[15:0]). M/R# is treated as an address line so that it can be controlled using system address A21. BS# (bus start) is not used and should be tied low (connected to GND). The PC Card interface does not provide a bus clock, so one must be supplied for the SED1354. Since the bus clock frequency is not critical, nor does it have to be synchronous to the bus signals, it may be the same as CLKI. The following diagram shows a typical implementation of the PC Card to SED1354 interface.
PC Card OE# WE# CE1# CE2# REG# RESET RESET# A21 M/R# A[21:0] D[15:0]
15K pull-up
PAL16L8-10
SED1354 RD# RD/WR# WE0# WE1# CS#
AB[20:0] DB[15:0] WAIT# BUSCLK Oscillator CLKI
WAIT#
Note: When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of PC Card to SED1354 Interface
Note
For pin mapping see Table 3-1: "Generic MPU Host Bus Interface Pin Mapping".
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 13
4.2 SED1354 Hardware Configuration
The SED1354 uses MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx. The tables below show only those configuration settings important to the PC Card interface. Table 4-1: Summary of Power-On/Reset Options
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 Little Endian WAIT# is active high (1 = insert wait state) = configuration for PC Card interface Big Endian WAIT# is active low (0 = insert wait state) For host bus interface selection see Table 4-2: "Host Bus Interface Selection" value on this pin at rising edge of RESET# is used to configure:(1/0) 1 8-bit host bus interface 16-bit host bus interface 0
Table 4-2: Host Bus Interface Selection
MD3 0 0 0 0 1 MD2 0 0 1 1 X MD1 0 1 0 1 X Host Bus Interface SH-3 MC68K Bus 1 (e.g. MC68000) MC68K Bus 2 (e.g. MC68030) Generic MPU Reserved
= configuration for PC Card interface
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 14
Epson Research and Development Vancouver Design Center
4.3 PAL Equations
The PAL equations used for the implementation presented in this document are as follows. Note that PALASM syntax uses positive logic. Active low pins are inverted in the pin declaration section.
CHIP PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PIN PCCAPP 1 2 3 4 5 6 12 13 14 15 16 17 10 20 PAL16L8 /oe /we /ce1 /ce2 /pcreg breset /we0 /we1 /cs /rd0 /rd1 /reset gnd vcc COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL ; ; ; ; ; ; ; ; ; ; ; ; bus bus bus bus bus bus read enable write enable low byte enable high byte enable CIS cycle enable reset (active high) low byte write high byte write chip select low byte read high byte read reset
SED1354 SED1354 SED1354 SED1354 SED1354 SED1354
; supply ; supply
EQUATIONS rd0 = oe * ce1 rd1 = oe * ce2 we0 = we * ce1 we1 = we * ce2 cs = rd0 + rd1 reset = breset * * * * + /pcreg /pcreg /pcreg /pcreg we0 + we1 ; ; ; ; /pcreg /pcreg /pcreg /pcreg means means means means disable disable disable disable in in in in attribute attribute attribute attribute mode mode mode mode
; inversion appears in pin declaration section
4.4 Register/Memory Mapping
The SED1354 is a memory mapped device. The internal registers are mapped in the lower PC Card memory address space starting at zero. The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card memory address space (ranging from 200000h to 3fffffh). The PC Card socket provides 64M bytes of address space. Without further resolution on the decoding logic (M/R# connected to A21), the entire register set is aliased for every 64 byte boundary within the specified address range above. Since address bits A[25:22] are ignored, the SED1355 registers and display buffer are aliased 16 times.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 15
5 Software
Test utilities and Windows(R) CE v2.0 display drivers are available for the SED1354. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1354CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The SED1354 test utilities and Windows CE v2.0 display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com.
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 16
Epson Research and Development Vancouver Design Center
6 References
6.1 Documents
* PCMCIA/JEIDA, PC Card Standard -- March 1997 * Epson Research and Development, Inc., SED1354 Hardware Functional Specification, Document Number X19A-A-002-xx. * Epson Research and Development, Inc., SED1354 Programming Notes and Examples, Document Number X19A-G-002-xx. * Epson Research and Development, Inc., SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx.
6.2 Document Sources
* PC Card Website: http://www.pc-card.com. * Epson Electronics America Website: http://www.eea.epson.com.
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 17
7 Technical Support
7.1 EPSON LCD/CRT Controllers (SED1354)
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
7.2 PC Card Standard
PCMCIA (Personal Computer Memory Card International Association) 2635 North First Street, Suite 209 San Jose, CA 95134 Tel: (408) 433-2273 Fax: (408) 433-9558 http://www.pc-card.com
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 X19A-G-009-04
Page 18
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-009-04
Interfacing to the PC Card Bus Issue Date: 99/03/10
SED1354 Color Graphics LCD/CRT Controller
Interfacing to the Toshiba MIPS TX3912 Processor
Document Number: X19A-G-012-03
Copyright (c) 1998, 1999 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
Page 2
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 3
Table of Contents
1 2 3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Interfacing to the TX3912 ................................8
SED1354 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . 9 3.2 Generic MPU Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . 10 Direct Connection to the Toshiba TX3912 4.1 Hardware Description . . . . . . . . 4.2 Memory Mapping and Aliasing . . . . 4.3 SED1354 Hardware Configuration . . . .. .. .. .. . . . . . . . . ... .. .. .. ... .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. ... .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. ... .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 11 12 13 14 14 16 18 19 20
4
5
System Design Using the IT8368E PC Card Buffer 5.1 Hardware Description--Using One IT8368E . . . 5.2 Hardware Description--Using Two IT8368E's . . 5.3 IT8368E Configuration . . . . . . . . . . . . 5.4 Memory Mapping and Aliasing . . . . . . . . 5.5 SED1354 Configuration . . . . . . . . . . .
6 7
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1 Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2 Document Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Technical Support . . . . . . . . . . . . . . 8.1 EPSON LCD/CRT Controllers (SED1354) . 8.2 Toshiba MIPS TX3912 Processor . . . . . 8.3 ITE IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . ... .. .. .. . . . . . . . . . . . . 23 23 23 23
8
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 4
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 5
List of Tables
Table 3-1: Table 4-1: Table 4-2: Table 5-1: Table 5-2: Table 5-3: Table 5-4: Generic MPU Host Bus Interface Pin Mapping . . . . . . . . . . SED1354 Configuration for Direct Connection . . . . . . . . . . SED1354 Host Bus Selection for Direct Connection . . . . . . . TX3912 to Unbuffered PC Card Slots System Address Mapping . TX3912 to PC Card Slots Address Remapping using the IT8368E SED1354 Configuration using the IT8368E . . . . . . . . . . . . SED1354 Host Bus Selection using the IT8368E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 13 13 19 19 20 20
List of Figures
Figure 4-1: Typical Implementation of TX3912 to SED1354 Direct Connection . . . . . . . . . . . 11 Figure 5-1: SED1354 to TX3912 Connection using One IT8368E . . . . . . . . . . . . . . . . . . . 15 Figure 5-2: SED1354 to TX3912 Connection using Two IT8368E . . . . . . . . . . . . . . . . . . 17
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 6
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 7
1 Introduction
This application note describes the hardware and software environment required to provide an interface between the SED1354 Color Graphics LCD/CRT Controller and the Toshiba TX3912 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at techpubs@erd.epson.com.
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 8
Epson Research and Development Vancouver Design Center
2 Interfacing to the TX3912
The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the SED1354 connects to the TX3912 processor. The SED1354 can be successfully interfaced using one of three configurations: * Direct connection to TX3912 (see Section 4, "Direct Connection to the Toshiba TX3912" on page 11). * System design using one ITE8368E PC Card/GPIO buffer chip (see Section 5.1, "Hardware Description--Using One IT8368E" on page 14). * System design using two ITE8368E PC Card/GPIO buffer chips (see Section 5.2, "Hardware Description--Using Two IT8368E's" on page 16).
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 9
3 SED1354 Host Bus Interface
The SED1354 implements a 16-bit Generic MPU host bus interface which is used to interface to the Toshiba TX3912 processor. The Generic MPU host bus interface is the least processor-specific interface mode supported by the SED1354 and was chosen to implement this interface due to the simplicity of its timing. The Generic MPU host bus interface is selected by the SED1354 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
Note
After reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh]) will be set to logic `1', meaning that the SED1354 will not respond to any host accesses until a write to REG[1Bh] clears this bit to 0. When debugging a new hardware design, this can sometimes give the appearance that the interface is not working, so it is important to remember to clear this bit before proceeding with debugging.
3.1 Generic MPU Host Bus Interface Pin Mapping
The following table shows the functions of each host bus interface signal. Table 3-1: Generic MPU Host Bus Interface Pin Mapping
SED1354 Pin Names AB[20:1] AB0 DB[15:0] WE1# M/R# CS# BUSCLK BS# RD/WR# RD# WE0# WAIT# RESET# Generic MPU A[20:1] A0 D[15:0] WE1# External Decode External Decode BCLK Connect to IO VDD RD1# RD0# WE0# WAIT# RESET#
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 10
Epson Research and Development Vancouver Design Center
3.2 Generic MPU Host Bus Interface Signals
The interface requires the following signals: * BUSCLK is a clock input which is required by the SED1354 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. * The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the CPU address and data bus, respectively. The hardware engineer must ensure that MD4 selects the proper endian mode upon reset. * M/R# (memory/register) may be considered an address line, allowing system address A21 to be connected to the M/R# line. * Chip Select (CS#) must be driven low whenever the SED1354 is accessed by the host CPU. * WE0# and WE1# are write enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is writing data to the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * RD# (RD0#) and RD/WR# (RD1#) are read enables for the low-order and high-order bytes, respectively, to be driven low when the host CPU is reading data from the SED1354. These signals must be generated by external hardware based on the control outputs from the host CPU. * WAIT# is a signal output from the SED1354 that indicates the host CPU must wait until data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU accesses to the SED1354 may occur asynchronously to the display update, it is possible that contention may occur in accessing the SED1354 internal registers and/or display buffer. The WAIT# line resolves these contentions by forcing the host to wait until the resource arbitration is complete. * The Bus Start (BS#) signal is not used for the Generic MPU host bus interface and should be tied low (connected to GND).
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 11
4 Direct Connection to the Toshiba TX3912
4.1 Hardware Description
The SED1354 is easily interfaced to the Toshiba TX3912 processor. In the direct connection implementation, the SED1354 occupies PC Card slot #1 of the TX3912. Although the address bus of the TX3912 is multiplexed, it can be demultiplexed using an advanced CMOS latch (e.g., 74ACT373). The direct connection implementation makes use of the Generic MPU host bus interface capability of the SED1354. The following diagram demonstrates a typical implementation of the TX3912 to SED1354 interface.
SED1354 TX3912 RD* WE* CARD1CSL* CARD1CSH*
+3.3V
IO VDD, CORE VDD RD0# RD1# WE0# WE1#
CS#
Latch
A23
System RESET
M/R# RESET# AB[20:13] AB[12:0] DB[7:0] DB[15:8]
ALE A[12:0] D[31:24] D[23:16] CARD1WAIT*
ENDIAN
A[20:13]
VDD
15K pull-up
See text
Clock divider
WAIT# BUSCLK CLKI
DCLKOUT
...or...
Oscillator
Note: When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that may reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of TX3912 to SED1354 Direct Connection
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 12
Epson Research and Development Vancouver Design Center
The host interface control signals of the SED1354 are asynchronous with respect to the SED1354 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum SED1354 clock frequencies. The SED1354 also has internal clock dividers providing additional flexibility.
4.2 Memory Mapping and Aliasing
The SED1354 requires an addressing space of 2M bytes for the display buffer and 64 bytes for the registers. This is divided into two address ranges by connecting A23 (demultiplexed from the TX3912) to the M/R# input of the SED1354. Using A23 makes this implementation software compatible with the two implementations that use the ITE IT8368E (see Section 5, "System Design Using the IT8368E PC Card Buffer" on page 14). All other addresses are ignored. The SED1354 address ranges, as seen by the TX3912 on the PC Card slot 1 memory space, are as follows: * 6400 0000h: SED1354 registers aliased 131,072 times at 64 byte intervals over 8M bytes. * 6480 0000h: SED1354 display buffer aliased 4 times at 2M byte intervals over 8M bytes. * 6500 0000h: SED1354 registers and display buffer, aliased another 3 times over 48M bytes. Since the TX3912 control signal CARDREG* is ignored, the SED1354 takes up the entire PC Card slot 1 configuration space. The address range is software compatible with both ITE IT8368E implementations. * 0900 0000h: SED1354 registers aliased 131,072 times at 64 byte intervals over 8M bytes. * 0980 0000h: SED1354 display buffer aliased 4 times at 2M byte intervals over 8M bytes.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 13
4.3 SED1354 Hardware Configuration
The SED1354 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Specification, document number X19A-A-002-xx. The partial table below shows those configuration settings relevant to the direct connection implementation. Table 4-1: SED1354 Configuration for Direct Connection
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 Little Endian WAIT# signal is active high Big Endian WAIT# signal is active low See "Host Bus Selection" table below See "Host Bus Selection" table below value on this pin at rising edge of RESET# is used to configure:(1/0) 1 8-bit host bus interface 0 16-bit host bus interface
= required configuration for direct connection with TX3912
Table 4-2: SED1354 Host Bus Selection for Direct Connection
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MCF5307, ISA bus interface) Reserved
= required configuration for direct connection with TX3912
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 14
Epson Research and Development Vancouver Design Center
5 System Design Using the IT8368E PC Card Buffer
If the system designer uses an ITE IT8368E PC Card and multiple-function IO buffer, the SED1354 can be interfaced with the TX3912 without using a PC Card slot. Instead, the SED1354 is mapped to a rarely-used 16M byte portion of the PC Card slot buffered by the IT8368E. This makes the SED1354 virtually transparent to PC Card devices that use the same slot.
5.1 Hardware Description--Using One IT8368E
The ITE IT8368E has been specifically designed to support EPSON CRT/LCD controllers. The IT8368E provides eleven Multi-Function IO pins (MFIO). Configuration registers can be used to allow these MFIO pins to provide the control signals required to implement the SED1354 CPU interface. The Toshiba TX3912 processor only provides addresses A[12:0], therefore devices that occupy more address space must use an external device to latch A[25:13]. The IT8368E's MFIO pins can be configured to provide this latched address. However, when using the SED1354, five MFIO pins are utilized for SED1354 control signals and cannot provide latched addresses. In this case, an external latch must be used to provide the high-order address bits. For a solution that does not require a latch, refer to Section 5.2, `Hardware Description--Using Two IT8368E's".
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 15
TX3912
A[12:0]
ENDIAN
SED1354
+3.3V
IO VDD, CORE VDD AB[12:0]
Latch
ALE D[31:24] D[23:16]
System RESET pull-up
AB[20:13] DB[7:0] DB[15:8] RESET# WAIT# A23 See text M/R# CLKI BUSCLK WE1# WE0# RD1# RD0#
VDD
CARDxWAIT* DCLKOUT
IT8368E
LHA23/MFIO10 LHA22/MFIO9 LHA21/MFIO8 LHA20/MFIO7 LHA19/MFIO6
Clock divider
...or... Oscillator
Chip Select Logic
CS#
Notes: The Chip Select Logic shown above is necessary to guarantee timing parameter t1 of the Generic MPU Interface Asynchronous Timing (for details refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx). When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that amy reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 5-1: SED1354 to TX3912 Connection using One IT8368E
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 16
Epson Research and Development Vancouver Design Center
The Generic MPU host interface control signals of the SED1354 are asynchronous with respect to the SED1354 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum SED1354 clock frequencies. The SED1354 also has internal clock dividers providing additional flexibility.
5.2 Hardware Description--Using Two IT8368E's
The following implementation uses a second IT8368E, not in VGA mode, in place of an address latch. The pins LHA23 and LHA[20:13] provide the latch function instead.
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 17
TX3912
A[12:0]
ENDIAN
SED1354
AB[12:0] AB[20:13]
D[31:24] D[23:16]
System RESET VDD pull-up
DB[7:0] DB[15:8] RESET# WAIT# LHA23
Clock divider
CARDxWAIT* DCLKOUT
M/R#
IT8368E
...or... Oscillator BUSCLK
LHA[20:13], LHA23
See text
CLKI
+3.3V
IO VDD, CORE VDD IT8368E LHA23/MFIO10 LHA22/MFIO9 LHA21/MFIO8 LHA20/MFIO7 LHA19/MFIO6 WE1# WE0# RD1# RD0# CS#
Chip Select Logic
Notes: The Chip Select Logic shown above is necessary to guarantee the timing parameter t1 of the Generic MPU Host Bus Interface Asynchronous Timing (for details refer to the SED1354 Hardware Functional Specification, document number X19A-A-002-xx). When connecting the SED1354 RESET# pin, the system designer should be aware of all conditions that amy reset the SED1354 (e.g. CPU reset can be asserted during wake-up from power-down modes, or during debug states).
Figure 5-2: SED1354 to TX3912 Connection using Two IT8368E
Note
For pin mapping see Table 3-1:, "Generic MPU Host Bus Interface Pin Mapping".
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 18
Epson Research and Development Vancouver Design Center
The Generic MPU host interface control signals of the SED1354 are asynchronous with respect to the SED1354 bus clock. This gives the system designer full flexibility in choosing the appropriate source (or sources) for CLKI and BUSCLK. Deciding whether both clocks should be the same and whether to use DCLKOUT (divided) as the clock source, should be based on the desired: * pixel and frame rates. * power budget. * part count. * maximum SED1354 clock frequencies. The SED1354 also has internal clock dividers providing additional flexibility.
5.3 IT8368E Configuration
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E (or the first in a two-IT8368E implementation) must have both "Fix Attribute/IO" and "VGA" modes on. When both these modes are enabled, the MFIO pins provide control signals needed by the SED1354 host bus interface, and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the SED1354. When accessing the SED1354 the associated card-side signals are disabled in order to avoid any conflicts.
Note
When a second IT8368E is used, it should not be set in VGA mode. For mapping details, refer to Section 5.4, `Memory Mapping and Aliasing" For further information on configuring the IT8368E, refer to the IT8368E PC Card/GPIO Buffer Chip Specification.
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 19
5.4 Memory Mapping and Aliasing
When the TX3912 accesses the PC Card slots without the ITE IT8368E, its system memory is mapped as in Table , "".
Note
Bits CARD1IOEN and CARD2IOEN need to be set in the TX3912 Memory Configuration Register 3. Table 5-1: TX3912 to Unbuffered PC Card Slots System Address Mapping
TX3912 Address 0800 0000h 0C00 0000h 6400 0000h 6400 0000h Size 64Mb 64Mb 64Mb 64Mb Function (CARDnIOEN=0) Card 1 Attribute Card 2 Attribute Card 1 Memory Card 2 Memory Function (CARDnIOEN=1) Card 1 IO Card 2 IO
When the TX3912 accesses the PC Card slots buffered through the ITE IT8368E, bits CARD1IOEN and CARD2IOEN are ignored and the attribute/IO space of the TX3912 is divided into Attribute, IO and SED1354 access. Table 5-2:, "TX3912 to PC Card Slots Address Remapping using the IT8368E" provides all the details of the Attribute/IO address re-allocation by the IT8368E. Table 5-2: TX3912 to PC Card Slots Address Remapping using the IT8368E
IT8368E Uses PC Card Slot # TX3912 Address 0800 0000h 0900 0000h 1 0980 0000h 0A00 0000h 6400 0000h 0C00 0000h 0D00 0000h 2 0D80 0000h 0E00 0000h 6800 0000h Size 16M byte 8M byte 8M byte 32M byte 64M byte 16M byte 8M byte 8M byte 32M byte 64M byte Function Card 1 IO SED1354 registers, aliased 131,072 times at 64 byte intervals SED1354 display buffer, aliased 4 times at 2Mb intervals Card 1 Attribute Card 1 Memory Card 2 IO SED1354 registers, aliased 131,072 times at 64 byte intervals SED1354 display buffer, aliased 4 times at 2Mb intervals Card 2 Attribute Card 2 Memory
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 20
Epson Research and Development Vancouver Design Center
5.5 SED1354 Configuration
The SED1354 latches MD0 through MD15 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the SED1354 Hardware Specification, document number X19A-A-002-xx. The partial table below only shows those configuration settings relevant to the IT8368E implementation. Table 5-3: SED1354 Configuration using the IT8368E
SED1354 Pin Name MD0 MD1 MD2 MD3 MD4 MD5 Little Endian WAIT# signal is active high Big Endian WAIT# signal is active low See "Host Bus Selection" table below See "Host Bus Selection" table below value on this pin at rising edge of RESET# is used to configure:(1/0) 1 8-bit host bus interface 0 16-bit host bus interface
= required configuration for connection using ITE IT8368E
Table 5-4: SED1354 Host Bus Selection using the IT8368E
MD3 0 0 0 0 1 MD2 0 0 1 1 x MD1 0 1 0 1 x Host Bus Interface SH-3 bus interface MC68K bus 1 interface (e.g. MC68000) MC68K bus 2 interface (e.g. MC68030) Generic bus interface (e.g. MCF5307, ISA bus interface) Reserved
= required configuration for connection using ITE IT8368E
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 21
6 Software
Test utilities and Windows(R) CE v2.0 display drivers are available for the SED1354. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 1354CFG, or by directly modifying the source. The Windows CE v2.0 display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source. The SED1354 test utilities and Windows CE v2.0 display drivers are available from your sales support contact or on the internet at http://www.eea.epson.com.
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 22
Epson Research and Development Vancouver Design Center
7 References
7.1 Documents
* Toshiba America Electrical Components, Inc., TX3905/12 Specification. * Epson Research and Development, Inc., SED1354 Color Graphics LCD/CRT Controller Hardware Functional Specification, Document Number X19A-A-002-xx. * Epson Research and Development, Inc., SDU1354B0C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-004-xx. * Epson Research and Development, Inc., SED1354 Programming Notes and Examples, Document Number X19A-G-002-xx.
7.2 Document Sources
* Toshiba America Electrical Components Website: http://www.toshiba.com/taec. * Epson Electronics America Website: http://www.eea.epson.com.
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
Epson Research and Development Vancouver Design Center
Page 23
8 Technical Support
8.1 EPSON LCD/CRT Controllers (SED1354)
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan, R.O.C. Tel: 02-2717-7360 Fax: 02-2712-9164 Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110
Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346
8.2 Toshiba MIPS TX3912 Processor
http://www.toshiba.com/taec/nonflash/indexproducts.html
8.3 ITE IT8368E
Integrated Technology Express, Inc. Sales & Marketing Division 2710 Walsh Avenue Santa Clara, CA 95051, USA Tel: (408) 980-8168 Fax: (408) 980-9232 http://www.iteusa.com
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10
SED1354 X19A-G-012-03
Page 24
Epson Research and Development Vancouver Design Center
THIS PAGE LEFT BLANK
SED1354 X19A-G-012-03
Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 99/03/10

▲Up To Search▲

Price & Availability of SED1354

	To Download SED1354 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .